Re: [Qemu-devel] [PATCH 03/14] target-mips: fix FPU exceptions

[Richard Henderson <rth@twiddle.net>]

On 10/09/2012 01:27 PM, Aurelien Jarno wrote:
> -    return float64_sqrt(fdt0, &env->active_fpu.fp_status);
> +    set_float_exception_flags(0, &env->active_fpu.fp_status);
> +    fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
> +    update_fcr31(env);
> +    return fdt0;

While accurate, I can't help but think there'd be less memory traffic
if the invariant "fp_status == 0" is maintained between insns.  Thus
you don't need to reset the flags to 0 in each insn, merely change

static inline void update_fcr31(CPUMIPSState *env)
{
    int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
    if (tmp) {
        set_float_exception_flags(0, &env->active_fpu.fp_status);
        SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
        if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
            helper_raise_exception(env, EXCP_FPE);
        } else {
            UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
        }
    }
}

I'll also note that we don't get the proper PC for the trap there.
We don't save the PC in the translator before the insn, or, more
properly invoke do_restore_state.  That clearly ought to be a
separate change, however.


r~