From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59359) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMR6s-0004xb-Eh for qemu-devel@nongnu.org; Thu, 11 Oct 2012 18:20:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TMR6r-0007mJ-7x for qemu-devel@nongnu.org; Thu, 11 Oct 2012 18:20:06 -0400 Received: from hub021-nj-1.exch021.serverdata.net ([206.225.164.216]:2904) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMR6r-0007fX-3f for qemu-devel@nongnu.org; Thu, 11 Oct 2012 18:20:05 -0400 Message-ID: <50774611.1020505@CloudSwitch.Com> Date: Thu, 11 Oct 2012 18:20:01 -0400 From: Don Slutz MIME-Version: 1.0 References: <1348497138-2516-1-git-send-email-Don@CloudSwitch.com> <1348497138-2516-4-git-send-email-Don@CloudSwitch.com> <20121009162520.GB12330@amt.cnet> <5074773F.6070503@CloudSwitch.Com> <507592C0.6030107@CloudSwitch.Com> <507596D2.2000505@suse.de> In-Reply-To: <507596D2.2000505@suse.de> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v6 03/16] target-i386: Add cpu object access routines for Hypervisor level. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-1?Q?Andreas_F=E4rber?= Cc: peter.maydell@linaro.org, ehabkost@redhat.com, kvm@vger.kernel.org, Marcelo Tosatti , qemu-devel@nongnu.org, avi@redhat.com, anthony@codemonkey.ws, Igor Mammedov On 10/10/12 11:40, Andreas F=E4rber wrote: > Am 10.10.2012 17:22, schrieb Don Slutz: >> On 10/09/12 15:13, Don Slutz wrote: >>> On 10/09/12 12:25, Marcelo Tosatti wrote: >>>> On Mon, Sep 24, 2012 at 10:32:05AM -0400, Don Slutz wrote: >>>>> +static void x86_cpuid_set_hv_level(Object *obj, Visitor *v, void >>>>> *opaque, >>>>> + const char *name, Error **errp) >>>>> +{ >>>>> + X86CPU *cpu =3D X86_CPU(obj); >>>>> + uint32_t value; >>>>> + >>>>> + visit_type_uint32(v, &value, name, errp); >>>>> + if (error_is_set(errp)) { >>>>> + return; >>>>> + } >>>>> + >>>>> + if (value !=3D 0 && value < 0x40000000) { >>>>> + value +=3D 0x40000000; >>>>> + } >>>> Whats the purpose of this? Adds ambiguity. > [...] >> This is direct copy with adjustment from x86_cpuid_set_xlevel(): >> >> if (value < 0x80000000) { >> value +=3D 0x80000000; >> } >> >> (Pending patch: >> http://comments.gmane.org/gmane.comp.emulators.qemu/172703 adds this) > (Any pending patch can be changed ;)) > >> The adjustment is that 0 is a legal value. See >> http://lkml.indiana.edu/hypermail/linux/kernel/1205.0/00100.html >> >> This does mean that just like xlevel=3D1 and xlevel=3D0x80000001 are the >> same; hypervisor-level=3D1 and hypervisor-level=3D0x4000001 are the same= . >> If this is not wanted, I have no issue with removing it. > I have no strong opinion either way, but if there's only one call site, > I'd prefer to apply these fixups to user input before setting the > property and to have the property setter error out on invalid values. I > consider that cleaner than silently fixing up values inside the setter. > > Regards, > Andreas > I find more then one call site. And one of them is converting the=20 predefined x86 cpus (like 486). So I am not planning on a change. I have finished up the v7 changes except for this. I will wait until=20 some time tomorrow to send it in case there is more on this topic. -Don Slutz