From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TQiCp-0002NX-7D for qemu-devel@nongnu.org; Tue, 23 Oct 2012 13:24:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TQiCi-0000hh-B8 for qemu-devel@nongnu.org; Tue, 23 Oct 2012 13:23:55 -0400 Received: from hub021-nj-2.exch021.serverdata.net ([206.225.164.217]:60992) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TQiCi-0000gr-6Y for qemu-devel@nongnu.org; Tue, 23 Oct 2012 13:23:48 -0400 Message-ID: <5086D29F.50209@CloudSwitch.Com> Date: Tue, 23 Oct 2012 13:23:43 -0400 From: Don Slutz MIME-Version: 1.0 References: <1350918203-25198-1-git-send-email-imammedo@redhat.com> <1350918203-25198-37-git-send-email-imammedo@redhat.com> In-Reply-To: <1350918203-25198-37-git-send-email-imammedo@redhat.com> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 36/37] target-i386: use static properties to list CPUID features List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov Cc: aliguori@us.ibm.com, ehabkost@redhat.com, jan.kiszka@siemens.com, mdroth@linux.vnet.ibm.com, qemu-devel@nongnu.org, blauwirbel@gmail.com, stefanha@redhat.com, pbonzini@redhat.com, afaerber@suse.de Turns out that patch #32 is the one that causes the command line: =2E/x86_64-softmmu/qemu-system-x86_64 -cpu=20 486,+fpu,+vme,+de,+pse,+tsc,+msr,+pae,+mce,+cx8,+apic,+sep,+mtrr,+pge,+mc= a,+cmov,+pat,+pse36,+pn,+clflush,+ds,+acpi,+mmx,+fxsr,+sse,+sse2,+ss,+ht,= +tm,+ia64,+pbe,+pni,+sse3,+pclmulqdq,+pclmuldq,+dtes64,+monitor,+ds_cpl,+= vmx,+smx,+est,+tm2,+ssse3,+cid,+fma,+cx16,+xtpr,+pdcm,+pcid,+dca,+sse4.1,= +sse4.2,+sse4_1,+sse4_2,+x2apic,+movbe,+popcnt,+tsc-deadline,+aes,+xsave,= +osxsave,+avx,+hypervisor,+syscall,+nx,+xd,+mmxext,+fxsr_opt,+ffxsr,+pdpe= 1gb,+rdtscp,+lahf_lm,+cmp_legacy,+svm,+extapic,+cr8legacy,+abm,+sse4a,+mi= salignsse,+3dnowprefetch,+osvw,+ibs,+xop,+skinit,+wdt,+fma4,+cvt16,+nodei= d_msr,+kvmclock1,+kvm_nopiodelay,+kvm_mmu,+kvmclock2,+kvm_asyncpf,+kvm_st= eal_tm,+kvm_pv_eoi,+kvmclock_stable,+npt,+lbrv,+svm_lock,+nrip_save,+tsc_= scale,+vmcb_clean,+flushbyasid,+decodeassists,+pause_filter,+pfthreshold,= +smep,+smap,family=3D6,model=3D23,stepping=3D10,level=3D13,xlevel=3D0x800= 00008,vendor=3D"GenuineIntel",model-id=3D"Intel(R)=20 Core(TM)2 Quad CPU Q9650 @=20 3.00GHz",+pbe,+tm,+ht,+ss,+sse2,+sse,+fxsr,+mmx,+acpi,+ds,+clflush,+pse36= ,+pat,+cmov,+mca,+pge,+mtrr,+sep,+apic,+cx8,+mce,+pae,+msr,+tsc,+pse,+de,= +vme,+fpu,+osxsave,+xsave,+sse4_1,+pdcm,+xtpr,+cx16,+ssse3,+tm2,+est,+smx= ,+vmx,+ds_cpl,+monitor,+dtes64,+sse3,+nx,+lahf_lm=20 ~/qemu-img/CentOS5-32.raw -cdrom=20 /isos/iso/centos/i386/CentOS-5.3-i386-bin-DVD.iso -machine pc,accel=3Dkvm= =20 -m 1024 -monitor stdio to stop allowing 64bit code to run. However this patch has the key info = (see below). On 10/22/12 11:03, Igor Mammedov wrote: > convert x86_cpu_list() to use QDEV_FIND_PROP_FROM_BIT() for getting > CPUID feature name. > In addition since x86_cpu_list() was the last user of *feature_name > arrays, clean them up. > > Signed-off-by: Igor Mammedov > --- > target-i386/cpu.c | 106 +++++++++++----------------------------------= --------- > 1 file changed, 20 insertions(+), 86 deletions(-) > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 89ef2a7..8d7718c 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -38,55 +38,6 @@ > #include > #endif > =20 > -/* feature flags taken from "Intel Processor Identification and the CP= UID > - * Instruction" and AMD's "CPUID Specification". In cases of disagree= ment > - * between feature naming conventions, aliases may be added. > - */ > -static const char *feature_name[] =3D { > - "fpu", "vme", "de", "pse", > - "tsc", "msr", "pae", "mce", > - "cx8", "apic", NULL, "sep", > - "mtrr", "pge", "mca", "cmov", > - "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,= > - NULL, "ds" /* Intel dts */, "acpi", "mmx", > - "fxsr", "sse", "sse2", "ss", > - "ht" /* Intel htt */, "tm", "ia64", "pbe", > -}; > -static const char *ext_feature_name[] =3D { > - "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "= monitor", > - "ds_cpl", "vmx", "smx", "est", > - "tm2", "ssse3", "cid", NULL, > - "fma", "cx16", "xtpr", "pdcm", > - NULL, "pcid", "dca", "sse4.1|sse4_1", > - "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", > - "tsc-deadline", "aes", "xsave", "osxsave", > - "avx", NULL, NULL, "hypervisor", > -}; > -/* Feature names that are already defined on feature_name[] but are se= t on > - * CPUID[8000_0001].EDX on AMD CPUs don't have their names on > - * ext2_feature_name[]. They are copied automatically to cpuid_ext2_fe= atures > - * if and only if CPU vendor is AMD. > - */ > -static const char *ext2_feature_name[] =3D { > - NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, > - NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, > - NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscal= l", > - NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, > - NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, > - "nx|xd", NULL, "mmxext", NULL /* mmx */, > - NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "r= dtscp", > -}; This array does not have 32 entries. And at least on my test machine=20 "+lahf_lm" sets ext2_feature bit 29 (and also ext3_feature bit 0). From http://www.sandpile.org/x86/cpuid.htm#level_8000_0001h bit 29 (LM) AMD64/EM64T, Long Mode bit 29 (LM) AMD64/EM64T, Long Mode (And the next 2 bits are defined as well: bit 30 (3DNow!+) extended 3DNow! bit 31 (3DNow!) 3DNow! ). Since master has this bug (feature?), I feel that access to ext2 bit 29=20 is needed ("f-lm" ?) -Don Slutz > -static const char *ext3_feature_name[] =3D { > - "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AM= D ExtApicSpace */, > - "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", > - "3dnowprefetch", "osvw", "ibs", "xop", > - "skinit", "wdt", NULL, NULL, > - "fma4", NULL, "cvt16", "nodeid_msr", > - NULL, NULL, NULL, NULL, > - NULL, NULL, NULL, NULL, > - NULL, NULL, NULL, NULL, > -}; > - > #if defined(CONFIG_KVM) > static void x86_cpu_get_kvmclock(Object *obj, Visitor *v, void *opaqu= e, > const char *name, Error **errp) > @@ -1495,35 +1446,22 @@ error: > return -1; > } > =20 > -/* generate a composite string into buf of all cpuid names in features= et > - * selected by fbits. indicate truncation at bufsize in the event of = overflow. > - * if flags, suppress names undefined in featureset. > - */ > -static void listflags(char *buf, int bufsize, uint32_t fbits, > - const char **featureset, uint32_t flags) > -{ > - const char **p =3D &featureset[31]; > - char *q, *b, bit; > - int nc; > - > - b =3D 4 <=3D bufsize ? buf + (bufsize -=3D 3) - 1 : NULL; > - *buf =3D '\0'; > - for (q =3D buf, bit =3D 31; fbits && bufsize; --p, fbits &=3D ~(1 = << bit), --bit) > - if (fbits & 1 << bit && (*p || !flags)) { > - if (*p) > - nc =3D snprintf(q, bufsize, "%s%s", q =3D=3D buf ? "" = : " ", *p); > - else > - nc =3D snprintf(q, bufsize, "%s[%d]", q =3D=3D buf ? "= " : " ", bit); > - if (bufsize <=3D nc) { > - if (b) { > - memcpy(b, "...", sizeof("...")); > - } > - return; > - } > - q +=3D nc; > - bufsize -=3D nc; > - } > -} > +#define LIST_FLAGS(_typename, _state, _field) \ > + do { \ > + int i; \ > + const Property *prop; \ > + const DeviceClass *dc; \ > + dc =3D DEVICE_CLASS(object_class_by_name((_typename))); \= > + (*cpu_fprintf)(f, " "); \ > + for (i =3D 31; i; --i) { \= > + prop =3D QDEV_FIND_PROP_FROM_BIT(dc, _state, _field, i); \= > + if (prop) { \ > + /* for compatibility do not print f- prefix */ \ > + (*cpu_fprintf)(f, " %s", prop->name + 2); \ > + } \ > + } \ > + (*cpu_fprintf)(f, "\n"); \ > + } while (0) > =20 > /* generate CPU information. */ > void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf) > @@ -1539,14 +1477,10 @@ void x86_cpu_list(FILE *f, fprintf_function cpu= _fprintf) > (*cpu_fprintf)(f, "x86 %16s\n", "[host]"); > } > (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n"); > - listflags(buf, sizeof(buf), (uint32_t)~0, feature_name, 1); > - (*cpu_fprintf)(f, " %s\n", buf); > - listflags(buf, sizeof(buf), (uint32_t)~0, ext_feature_name, 1); > - (*cpu_fprintf)(f, " %s\n", buf); > - listflags(buf, sizeof(buf), (uint32_t)~0, ext2_feature_name, 1); > - (*cpu_fprintf)(f, " %s\n", buf); > - listflags(buf, sizeof(buf), (uint32_t)~0, ext3_feature_name, 1); > - (*cpu_fprintf)(f, " %s\n", buf); > + LIST_FLAGS(TYPE_X86_CPU, CPUX86State, cpuid_features); > + LIST_FLAGS(TYPE_X86_CPU, CPUX86State, cpuid_ext_features); > + LIST_FLAGS(TYPE_X86_CPU, CPUX86State, cpuid_ext2_features); > + LIST_FLAGS(TYPE_X86_CPU, CPUX86State, cpuid_ext3_features); > } > =20 > CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)