From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59483) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRMBA-0008EZ-TA for qemu-devel@nongnu.org; Thu, 25 Oct 2012 08:04:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TRMB5-0004ye-3S for qemu-devel@nongnu.org; Thu, 25 Oct 2012 08:04:52 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45247) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TRMB4-0004ya-RK for qemu-devel@nongnu.org; Thu, 25 Oct 2012 08:04:47 -0400 Message-ID: <50892AD8.70205@redhat.com> Date: Thu, 25 Oct 2012 14:04:40 +0200 From: Gerd Hoffmann MIME-Version: 1.0 References: <9e7120500a1322214fe5cb90ba716c90c23af441.1351157627.git.peter.crosthwaite@xilinx.com> In-Reply-To: <9e7120500a1322214fe5cb90ba716c90c23af441.1351157627.git.peter.crosthwaite@xilinx.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v1 1/8] usb/ehci: parameterise the register region offsets List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: vineshp@xilinx.com, edgar.iglesias@gmail.com, john.williams@xilinx.com, qemu-devel@nongnu.org, peter.maydell@linaro.org On 10/25/12 11:47, Peter Crosthwaite wrote: > The capabilities register and operational register offsets can vary from one > EHCI implementation to the next. Parameterise accordingly. > static Property ehci_properties[] = { > DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), > + DEFINE_PROP_UINT16("capabase", EHCIState, capabase, 0), > + DEFINE_PROP_UINT16("opregbase", EHCIState, opregbase, 0x20), > DEFINE_PROP_END_OF_LIST(), > }; I don't think we want have this as properties. Just set them in initfn(). > @@ -2718,8 +2719,10 @@ static int usb_ehci_initfn(PCIDevice *dev) > pci_conf[0x6e] = 0x00; > pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS > > + s->caps = g_malloc0(s->opregbase); I don't think we need to make that dynamic. opregbase just happened equal caps_size for pci-ehci due to packing these regions without space inbetween. > memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, > - "capabilities", OPREGBASE); > + "capabilities", s->opregbase); caps_size cheers, Gerd