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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21105706891sm66442295ad.69.2024.11.04.14.23.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Nov 2024 14:23:56 -0800 (PST) Message-ID: <508f34c0-c5fd-4f41-9aba-4c2735b12f5e@linaro.org> Date: Mon, 4 Nov 2024 14:23:55 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hw/riscv: fix build error with clang Content-Language: en-US To: qemu-devel@nongnu.org Cc: Cleber Rosa , qemu-riscv@nongnu.org, Liu Zhiwei , Mahmoud Mandour , Alistair Francis , John Snow , Stefano Garzarella , Thomas Huth , =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , "Michael S. Tsirkin" , Weiwei Li , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Konstantin Kostiuk , Bin Meng , Paolo Bonzini , Alexandre Iooss , Michael Roth , =?UTF-8?Q?Alex_Benn=C3=A9e?= , =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , Palmer Dabbelt References: <20241101170833.1074954-1-pierrick.bouvier@linaro.org> From: Pierrick Bouvier In-Reply-To: <20241101170833.1074954-1-pierrick.bouvier@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/1/24 10:08, Pierrick Bouvier wrote: > Introduced in 0c54ac, "hw/riscv: add RISC-V IOMMU base emulation" > > ../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64' > > 187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext) > > | ^ > > D:/a/_temp/msys64/clang64/lib/clang/18/include/bmi2intrin.h:217:1: note: previous definition is here > > 217 | _pext_u64(unsigned long long __X, unsigned long long __Y) > > | ^ > > Signed-off-by: Pierrick Bouvier > --- > hw/riscv/riscv-iommu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index feb650549ac..f738570bac2 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -184,7 +184,7 @@ static void riscv_iommu_pri(RISCVIOMMUState *s, > } > > /* Portable implementation of pext_u64, bit-mask extraction. */ > -static uint64_t _pext_u64(uint64_t val, uint64_t ext) > +static uint64_t pext_u64(uint64_t val, uint64_t ext) > { > uint64_t ret = 0; > uint64_t rot = 1; > @@ -528,7 +528,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s, > int cause; > > /* Interrupt File Number */ > - intn = _pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask); > + intn = pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask); > if (intn >= 256) { > /* Interrupt file number out of range */ > res = MEMTX_ACCESS_ERROR; Sent v2 with changes asked in this thread.