From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45414) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTGRb-0000Y8-L3 for qemu-devel@nongnu.org; Tue, 30 Oct 2012 14:21:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TTGRX-00033t-4p for qemu-devel@nongnu.org; Tue, 30 Oct 2012 14:21:43 -0400 Received: from mout.web.de ([212.227.17.11]:58917) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTGRW-00033g-QA for qemu-devel@nongnu.org; Tue, 30 Oct 2012 14:21:39 -0400 Message-ID: <50901AAE.4010802@web.de> Date: Tue, 30 Oct 2012 19:21:34 +0100 From: Jan Kiszka MIME-Version: 1.0 References: <1351599394-24876-1-git-send-email-pbonzini@redhat.com> <1351599394-24876-4-git-send-email-pbonzini@redhat.com> <508FCA33.5030309@redhat.com> <508FE140.2000302@redhat.com> In-Reply-To: <508FE140.2000302@redhat.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig6F6BB29DE8156564DE850C92" Subject: Re: [Qemu-devel] [PATCH 3/3] apic: always update the in-kernel status after loading List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: mtosatti@redhat.com, Avi Kivity , kvm@vger.kernel.org, qemu-devel@nongnu.org This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig6F6BB29DE8156564DE850C92 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable On 2012-10-30 15:16, Paolo Bonzini wrote: > Il 30/10/2012 13:38, Avi Kivity ha scritto: >> On 10/30/2012 02:16 PM, Paolo Bonzini wrote: >>> The LAPIC is loaded separately from the rest of the VCPU state. Thus= , >>> when restoring the CPU the dummy post-reset state is passed to the >>> in-kernel APIC. >>> >>> This can cause MSI injection to fail if attempted during the restore = of >>> another device, because the LAPIC believes it's not enabled. >>> >>> Signed-off-by: Paolo Bonzini >>> --- >>> hw/apic_common.c | 1 + >>> 1 files changed, 1 insertions(+), 0 deletions(-) >>> >>> diff --git a/hw/apic_common.c b/hw/apic_common.c >>> index f373ba8..1ef52b2 100644 >>> --- a/hw/apic_common.c >>> +++ b/hw/apic_common.c >>> @@ -362,6 +362,7 @@ static int apic_dispatch_post_load(void *opaque, = int version_id) >>> if (info->post_load) { >>> info->post_load(s); >>> } >>> + cpu_put_apic_state(DEVICE(s)); >>> return 0; >>> } >> >> Aren't we still dependent on the order of processing? If the APIC is >> restored after the device, won't we get the same problem? >=20 > Strictly speaking yes, but CPUs and APICs are always the first devices > to be saved. Hmm, thinking about this again: Why is the MSI event injected at all during restore, specifically while the device models are in transitional state. Can you explain this? Does the same pattern then also apply on INTx injection? Jan --------------enig6F6BB29DE8156564DE850C92 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.16 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://www.enigmail.net/ iEYEARECAAYFAlCQGq4ACgkQitSsb3rl5xSRcgCZAUEbHTSkXIG+GAcrK3ouDa0X OCMAoLGgrwB4SIxbx+jBZnaN/ishBn5g =2in4 -----END PGP SIGNATURE----- --------------enig6F6BB29DE8156564DE850C92--