Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Jovanovic, Petar]

+        case OPC_REPL_PH:
+            check_dsp(ctx);
+            {
+                imm = (ctx->opcode >> 16) & 0x03FF;
+                tcg_gen_movi_tl(cpu_gpr[ret], \
+                                (target_long)((int32_t)imm << 16 | \
+                                (uint32_t)(uint16_t)imm));
+            }

10-bit integer in REPL.PH is signed, so this code will not work for negative
values.
You need to sign-extend it, e.g. something like this:

+                imm = (ctx->opcode >> 16) & 0x03FF;
+                if (imm & (1 << 9)) {
+                  /* imm is negative, sign-extend it to 16 bits. */
+                  imm |= 0xFC00;
+                } 
+                tcg_gen_movi_tl(cpu_gpr[ret], \
+                                (target_long)((int32_t)imm << 16 | \
+                                (uint32_t)(uint16_t)imm));

As far as I can see, the test cases for REPL.PH in
tests/tcg/mips/mips32-dsp/repl_ph.c cover only positive values.
Make sure you include test cases for negative values as well.

Petar

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Jia Liu]

Hi Petar,

On Sun, Oct 28, 2012 at 6:58 AM, Jovanovic, Petar <petarj@mips.com> wrote:
> +        case OPC_REPL_PH:
> +            check_dsp(ctx);
> +            {
> +                imm = (ctx->opcode >> 16) & 0x03FF;
> +                tcg_gen_movi_tl(cpu_gpr[ret], \
> +                                (target_long)((int32_t)imm << 16 | \
> +                                (uint32_t)(uint16_t)imm));
> +            }
>
> 10-bit integer in REPL.PH is signed, so this code will not work for negative
> values.
> You need to sign-extend it, e.g. something like this:
>
> +                imm = (ctx->opcode >> 16) & 0x03FF;
> +                if (imm & (1 << 9)) {
> +                  /* imm is negative, sign-extend it to 16 bits. */
> +                  imm |= 0xFC00;
> +                }
> +                tcg_gen_movi_tl(cpu_gpr[ret], \
> +                                (target_long)((int32_t)imm << 16 | \
> +                                (uint32_t)(uint16_t)imm));
>
> As far as I can see, the test cases for REPL.PH in
> tests/tcg/mips/mips32-dsp/repl_ph.c cover only positive values.
> Make sure you include test cases for negative values as well.
>
> Petar

New code:
        case OPC_REPL_PH:
            check_dsp(ctx);
            {
                imm = (ctx->opcode >> 16) & 0x03FF;
                imm = (int16_t)(imm << 6) >> 6;
                tcg_gen_movi_tl(cpu_gpr[ret], \
                                (target_long)(int32_t)((int32_t)imm << 16 | \
                                (uint32_t)(uint16_t)imm));
            }
            break;

And the new test:
#include<stdio.h>
#include<assert.h>

int main()
{
    int rd, result;

    result = 0x01BF01BF;
    __asm
        ("repl.ph %0, 0x1BF\n\t"
         : "=r"(rd)
        );
    assert(rd == result);

    result = 0xFFFFFFFF;
    __asm
        ("repl.ph %0, -1\n\t"
         : "=r"(rd)
        );
    assert(rd == result);

    return 0;
}

is it OK?
And the other tests have be fixed.

Regards,
Jia.

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Jovanovic, Petar]

Hi Jia,

> imm = (int16_t)(imm << 6) >> 6;

result of a bitwise shift of a signed type and a negative vlaue is
implementation-defined, so you can not rely on that.

Regards,
Petar
________________________________________
From: Jia Liu [proljc@gmail.com]
Sent: Monday, October 29, 2012 1:36 PM
To: Jovanovic, Petar
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

Hi Petar,

On Sun, Oct 28, 2012 at 6:58 AM, Jovanovic, Petar <petarj@mips.com> wrote:
> +        case OPC_REPL_PH:
> +            check_dsp(ctx);
> +            {
> +                imm = (ctx->opcode >> 16) & 0x03FF;
> +                tcg_gen_movi_tl(cpu_gpr[ret], \
> +                                (target_long)((int32_t)imm << 16 | \
> +                                (uint32_t)(uint16_t)imm));
> +            }
>
> 10-bit integer in REPL.PH is signed, so this code will not work for negative
> values.
> You need to sign-extend it, e.g. something like this:
>
> +                imm = (ctx->opcode >> 16) & 0x03FF;
> +                if (imm & (1 << 9)) {
> +                  /* imm is negative, sign-extend it to 16 bits. */
> +                  imm |= 0xFC00;
> +                }
> +                tcg_gen_movi_tl(cpu_gpr[ret], \
> +                                (target_long)((int32_t)imm << 16 | \
> +                                (uint32_t)(uint16_t)imm));
>
> As far as I can see, the test cases for REPL.PH in
> tests/tcg/mips/mips32-dsp/repl_ph.c cover only positive values.
> Make sure you include test cases for negative values as well.
>
> Petar

New code:
        case OPC_REPL_PH:
            check_dsp(ctx);
            {
                imm = (ctx->opcode >> 16) & 0x03FF;
                imm = (int16_t)(imm << 6) >> 6;
                tcg_gen_movi_tl(cpu_gpr[ret], \
                                (target_long)(int32_t)((int32_t)imm << 16 | \
                                (uint32_t)(uint16_t)imm));
            }
            break;

And the new test:
#include<stdio.h>
#include<assert.h>

int main()
{
    int rd, result;

    result = 0x01BF01BF;
    __asm
        ("repl.ph %0, 0x1BF\n\t"
         : "=r"(rd)
        );
    assert(rd == result);

    result = 0xFFFFFFFF;
    __asm
        ("repl.ph %0, -1\n\t"
         : "=r"(rd)
        );
    assert(rd == result);

    return 0;
}

is it OK?
And the other tests have be fixed.

Regards,
Jia.

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Jia Liu]

Hi Petar,

On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
> Hi Jia,
>
>> imm = (int16_t)(imm << 6) >> 6;
>
> result of a bitwise shift of a signed type and a negative vlaue is
> implementation-defined, so you can not rely on that.
>

I think it will take a 10bits signed value sign extend into 16bits
signed value, and I've tested it with negative values, it working
well.

> Regards,
> Petar

Regards,
Jia.

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Peter Maydell]

On 30 October 2012 15:34, Jia Liu <proljc@gmail.com> wrote:
> On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
>>> imm = (int16_t)(imm << 6) >> 6;
>>
>> result of a bitwise shift of a signed type and a negative vlaue is
>> implementation-defined, so you can not rely on that.
>>
>
> I think it will take a 10bits signed value sign extend into 16bits
> signed value, and I've tested it with negative values, it working
> well.

You cannot rely on the behaviour of a specific compiler implementation
as evidence that a piece of code is correct. C has a standard which
defines what is and is not valid.

Having said that, right shift of negative signed integers is one of
those bits of implementation defined behaviour which we allow ourselves
to rely on in QEMU because all the platforms we care about behave
that way. (That integers are 2s complement representation is another.)

-- PMM

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Richard Henderson]

On 2012-10-31 01:44, Peter Maydell wrote:
> On 30 October 2012 15:34, Jia Liu <proljc@gmail.com> wrote:
>> On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
>>>> imm = (int16_t)(imm << 6) >> 6;
>>>
>>> result of a bitwise shift of a signed type and a negative vlaue is
>>> implementation-defined, so you can not rely on that.
>>>
>>
>> I think it will take a 10bits signed value sign extend into 16bits
>> signed value, and I've tested it with negative values, it working
>> well.
> 
> You cannot rely on the behaviour of a specific compiler implementation
> as evidence that a piece of code is correct. C has a standard which
> defines what is and is not valid.

Indeed.  The only portable way is

  val = ((val & (sign | (sign - 1))) ^ sign) - sign

with all unsigned types, and "sign" set to the sign bit.

> 
> Having said that, right shift of negative signed integers is one of
> those bits of implementation defined behaviour which we allow ourselves
> to rely on in QEMU because all the platforms we care about behave
> that way. (That integers are 2s complement representation is another.)

Also very true.  I don't like seeing the code in question though.
We've several implementations of sign-extend-to-N-bits functions
throughout qemu; we ought to unify them.


r~

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Jia Liu]

Hi Richard Peter Jovanovic and Aurelien,

On Wed, Oct 31, 2012 at 1:26 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 2012-10-31 01:44, Peter Maydell wrote:
>> On 30 October 2012 15:34, Jia Liu <proljc@gmail.com> wrote:
>>> On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
>>>>> imm = (int16_t)(imm << 6) >> 6;
>>>>
>>>> result of a bitwise shift of a signed type and a negative vlaue is
>>>> implementation-defined, so you can not rely on that.
>>>>
>>>
>>> I think it will take a 10bits signed value sign extend into 16bits
>>> signed value, and I've tested it with negative values, it working
>>> well.
>>
>> You cannot rely on the behaviour of a specific compiler implementation
>> as evidence that a piece of code is correct. C has a standard which
>> defines what is and is not valid.
>
> Indeed.  The only portable way is
>
>   val = ((val & (sign | (sign - 1))) ^ sign) - sign
>
> with all unsigned types, and "sign" set to the sign bit.
>

Thank you very much for the code.

Is this time OK?

static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
                                uint32_t op1, uint32_t op2,
                                int ret, int val)
{
    const char *opn = "mipsdsp Bit/ Manipulation";
    TCGv t0;
    TCGv val_t;

    if (ret == 0) {
        /* Treat as NOP. */
        MIPS_DEBUG("NOP");
        return;
    }

    t0 = tcg_temp_new();
    val_t = tcg_temp_new();
    gen_load_gpr(val_t, val);

#define SIGN_EXTEND10_16(val, sign) \
    val = (((val & (sign | (sign - 1))) ^ sign) - sign)

    switch (op1) {
    case OPC_ABSQ_S_PH_DSP:
        switch (op2) {
        case OPC_BITREV:
            check_dsp(ctx);
            gen_helper_bitrev(cpu_gpr[ret], val_t);
            break;
        case OPC_REPL_QB:
            check_dsp(ctx);
            {
                uint32_t imm;
                target_long result;

                imm = (ctx->opcode >> 16) & 0xFF;
                result = imm << 24 | imm << 16 | imm << 8  | imm;
                result = (int32_t)result;
                tcg_gen_movi_tl(cpu_gpr[ret], result);
            }
            break;
        case OPC_REPLV_QB:
            check_dsp(ctx);
            tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
            break;
        case OPC_REPL_PH:
            check_dsp(ctx);
            {
                uint16_t imm;
                imm = (ctx->opcode >> 16) & 0x03FF;
                SIGN_EXTEND10_16(imm, 0x200);
                tcg_gen_movi_tl(cpu_gpr[ret],
                                (target_long)(int32_t)
                                ((uint32_t)imm << 16 | imm));
            }
            break;
        case OPC_REPLV_PH:
            check_dsp(ctx);
            tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
            break;
        }
        break;
#ifdef TARGET_MIPS64
    case OPC_ABSQ_S_QH_DSP:
        switch (op2) {
        case OPC_REPL_OB:
            check_dsp(ctx);
            {
                target_ulong imm;

                imm = (ctx->opcode >> 16) & 0xFF;
                imm = (imm << 8) | imm;
                imm = (imm << 16) | imm;
                imm = (imm << 32) | imm;
                tcg_gen_movi_tl(cpu_gpr[ret], imm);
                break;
            }
        case OPC_REPL_PW:
            check_dsp(ctx);
            {
                target_long imm;

                imm = (ctx->opcode >> 16) & 0x03FF;
                SIGN_EXTEND10_16(imm, 0x200);
                tcg_gen_movi_tl(cpu_gpr[ret],
                                (imm << 32) | (imm & 0xFFFFFFFF));
                break;
            }
        case OPC_REPL_QH:
            check_dsp(ctx);
            {
                target_ulong imm;

                imm = (ctx->opcode >> 16) & 0x03FF;
                SIGN_EXTEND10_16(imm, 0x200);

                imm = imm & 0xFFFF;
                imm = (imm << 48) | (imm << 32) | (imm << 16) | imm;
                tcg_gen_movi_tl(cpu_gpr[ret], imm);
                break;
            }
        case OPC_REPLV_OB:
            check_dsp(ctx);
            tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            break;
        case OPC_REPLV_PW:
            check_dsp(ctx);
            tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            break;
        case OPC_REPLV_QH:
            check_dsp(ctx);
            tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
            break;
        }
        break;
#endif
    }

#undef SIGN_EXTEND10_16
    tcg_temp_free(t0);
    tcg_temp_free(val_t);

    (void)opn; /* avoid a compiler warning */
    MIPS_DEBUG("%s", opn);
}


>>
>> Having said that, right shift of negative signed integers is one of
>> those bits of implementation defined behaviour which we allow ourselves
>> to rely on in QEMU because all the platforms we care about behave
>> that way. (That integers are 2s complement representation is another.)
>
> Also very true.  I don't like seeing the code in question though.
> We've several implementations of sign-extend-to-N-bits functions
> throughout qemu; we ought to unify them.
>
>
> r~

Regards,
Jia.

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Aurelien Jarno]

On Wed, Oct 31, 2012 at 09:29:30PM +0800, Jia Liu wrote:
> Hi Richard Peter Jovanovic and Aurelien,
> 
> On Wed, Oct 31, 2012 at 1:26 PM, Richard Henderson <rth@twiddle.net> wrote:
> > On 2012-10-31 01:44, Peter Maydell wrote:
> >> On 30 October 2012 15:34, Jia Liu <proljc@gmail.com> wrote:
> >>> On Mon, Oct 29, 2012 at 9:40 PM, Jovanovic, Petar <petarj@mips.com> wrote:
> >>>>> imm = (int16_t)(imm << 6) >> 6;
> >>>>
> >>>> result of a bitwise shift of a signed type and a negative vlaue is
> >>>> implementation-defined, so you can not rely on that.
> >>>>
> >>>
> >>> I think it will take a 10bits signed value sign extend into 16bits
> >>> signed value, and I've tested it with negative values, it working
> >>> well.
> >>
> >> You cannot rely on the behaviour of a specific compiler implementation
> >> as evidence that a piece of code is correct. C has a standard which
> >> defines what is and is not valid.
> >
> > Indeed.  The only portable way is
> >
> >   val = ((val & (sign | (sign - 1))) ^ sign) - sign
> >
> > with all unsigned types, and "sign" set to the sign bit.
> >
> 
> Thank you very much for the code.
> 
> Is this time OK?

As said by Peter, I don't think the code should be modified, the
previous code was fine.

> static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
>                                 uint32_t op1, uint32_t op2,
>                                 int ret, int val)
> {
>     const char *opn = "mipsdsp Bit/ Manipulation";
>     TCGv t0;
>     TCGv val_t;
> 
>     if (ret == 0) {
>         /* Treat as NOP. */
>         MIPS_DEBUG("NOP");
>         return;
>     }
> 
>     t0 = tcg_temp_new();
>     val_t = tcg_temp_new();
>     gen_load_gpr(val_t, val);
> 
> #define SIGN_EXTEND10_16(val, sign) \
>     val = (((val & (sign | (sign - 1))) ^ sign) - sign)
> 
>     switch (op1) {
>     case OPC_ABSQ_S_PH_DSP:
>         switch (op2) {
>         case OPC_BITREV:
>             check_dsp(ctx);
>             gen_helper_bitrev(cpu_gpr[ret], val_t);
>             break;
>         case OPC_REPL_QB:
>             check_dsp(ctx);
>             {
>                 uint32_t imm;
>                 target_long result;
> 
>                 imm = (ctx->opcode >> 16) & 0xFF;
>                 result = imm << 24 | imm << 16 | imm << 8  | imm;
>                 result = (int32_t)result;
>                 tcg_gen_movi_tl(cpu_gpr[ret], result);
>             }
>             break;
>         case OPC_REPLV_QB:
>             check_dsp(ctx);
>             tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
>             break;
>         case OPC_REPL_PH:
>             check_dsp(ctx);
>             {
>                 uint16_t imm;
>                 imm = (ctx->opcode >> 16) & 0x03FF;
>                 SIGN_EXTEND10_16(imm, 0x200);
>                 tcg_gen_movi_tl(cpu_gpr[ret],
>                                 (target_long)(int32_t)
>                                 ((uint32_t)imm << 16 | imm));
>             }
>             break;
>         case OPC_REPLV_PH:
>             check_dsp(ctx);
>             tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
>             break;
>         }
>         break;
> #ifdef TARGET_MIPS64
>     case OPC_ABSQ_S_QH_DSP:
>         switch (op2) {
>         case OPC_REPL_OB:
>             check_dsp(ctx);
>             {
>                 target_ulong imm;
> 
>                 imm = (ctx->opcode >> 16) & 0xFF;
>                 imm = (imm << 8) | imm;
>                 imm = (imm << 16) | imm;
>                 imm = (imm << 32) | imm;
>                 tcg_gen_movi_tl(cpu_gpr[ret], imm);
>                 break;
>             }
>         case OPC_REPL_PW:
>             check_dsp(ctx);
>             {
>                 target_long imm;
> 
>                 imm = (ctx->opcode >> 16) & 0x03FF;
>                 SIGN_EXTEND10_16(imm, 0x200);
>                 tcg_gen_movi_tl(cpu_gpr[ret],
>                                 (imm << 32) | (imm & 0xFFFFFFFF));
>                 break;
>             }
>         case OPC_REPL_QH:
>             check_dsp(ctx);
>             {
>                 target_ulong imm;
> 
>                 imm = (ctx->opcode >> 16) & 0x03FF;
>                 SIGN_EXTEND10_16(imm, 0x200);
> 
>                 imm = imm & 0xFFFF;
>                 imm = (imm << 48) | (imm << 32) | (imm << 16) | imm;
>                 tcg_gen_movi_tl(cpu_gpr[ret], imm);
>                 break;
>             }
>         case OPC_REPLV_OB:
>             check_dsp(ctx);
>             tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             break;
>         case OPC_REPLV_PW:
>             check_dsp(ctx);
>             tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             break;
>         case OPC_REPLV_QH:
>             check_dsp(ctx);
>             tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
>             tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
>             break;
>         }
>         break;
> #endif
>     }
> 
> #undef SIGN_EXTEND10_16
>     tcg_temp_free(t0);
>     tcg_temp_free(val_t);
> 
>     (void)opn; /* avoid a compiler warning */
>     MIPS_DEBUG("%s", opn);
> }
> 
> 
> >>
> >> Having said that, right shift of negative signed integers is one of
> >> those bits of implementation defined behaviour which we allow ourselves
> >> to rely on in QEMU because all the platforms we care about behave
> >> that way. (That integers are 2s complement representation is another.)
> >
> > Also very true.  I don't like seeing the code in question though.
> > We've several implementations of sign-extend-to-N-bits functions
> > throughout qemu; we ought to unify them.
> >
> >
> > r~
> 
> Regards,
> Jia.
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Jia Liu]

Hi Aurelien,

On Thu, Nov 1, 2012 at 3:20 AM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Wed, Oct 31, 2012 at 09:29:30PM +0800, Jia Liu wrote:
>>
>> Is this time OK?
>
> As said by Peter, I don't think the code should be modified, the
> previous code was fine.
>

You mean my v12 09/14 is OK? It is a good news to me:D

>>
>> Regards,
>> Jia.
>>
>>
>
> --
> Aurelien Jarno                          GPG: 1024D/F1BCDB73
> aurelien@aurel32.net                 http://www.aurel32.net

Regards,
Jia.

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Jovanovic, Petar]

Since the change has been committed as-is, who will be sending fixes for OPC_REPL_PH and other cases?
Jia, will you do that?

Regards,
Petar
________________________________________
From: Jia Liu [proljc@gmail.com]
Sent: Thursday, November 01, 2012 1:34 AM
To: Aurelien Jarno
Cc: Richard Henderson; Peter Maydell; Jovanovic, Petar; qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

Hi Aurelien,

On Thu, Nov 1, 2012 at 3:20 AM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> On Wed, Oct 31, 2012 at 09:29:30PM +0800, Jia Liu wrote:
>>
>> Is this time OK?
>
> As said by Peter, I don't think the code should be modified, the
> previous code was fine.
>

You mean my v12 09/14 is OK? It is a good news to me:D

>>
>> Regards,
>> Jia.
>>
>>
>
> --
> Aurelien Jarno                          GPG: 1024D/F1BCDB73
> aurelien@aurel32.net                 http://www.aurel32.net

Regards,
Jia.

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Aurelien Jarno]

On Tue, Nov 06, 2012 at 03:50:08AM +0000, Jovanovic, Petar wrote:
> Since the change has been committed as-is, who will be sending fixes for OPC_REPL_PH and other cases?
> Jia, will you do that?
> 

I am working on a patch series fixing and cleaning DSP support, it will
include this fix. I hope to post it before the end of the week.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Peter Maydell]

On 29 October 2012 13:36, Jia Liu <proljc@gmail.com> wrote:
>         case OPC_REPL_PH:
>             check_dsp(ctx);
>             {
>                 imm = (ctx->opcode >> 16) & 0x03FF;
>                 imm = (int16_t)(imm << 6) >> 6;
>                 tcg_gen_movi_tl(cpu_gpr[ret], \
>                                 (target_long)(int32_t)((int32_t)imm << 16 | \
>                                 (uint32_t)(uint16_t)imm));
>             }
>             break;

This code is using rather more casts than it needs to.
Also, if you kept the scope of 'imm' to the local blocks
where it is used then it would be easy to see at a glance
what type it is (in this case int16_t) and thus which
of these casts are needed. (It would also mean you could
use the sensible type for the job -- for instance
in the OPC_REPL_QB case a 32 bit type would let you
avoid a lot of the casts your current code has.)

-- PMM

[Qemu-devel] [PATCH v12 00/14] QEMU MIPS ASE DSP support

[Jia Liu]

This is MIPS ASE DSP instructions support for QEMU. These instructions
are grouped according to "Chapter 4. MIPS DSP ASE Instruction Summary"
in MIPS ASE DSP manual [1][2].

[1] MIPS32® Architecture for Programmers VolumeIV-e: The MIPS® DSP
    Application-Specific Extension to the MIPS32®Architecture
    http://www.mips.com/products/product-materials/processor/mips-architecture/

[2] MIPS64® Architecture for Programmers VolumeIV-e: The MIPS® DSP
    Application-Specific Extention to the MIPS64® Architecture
    http://www.mips.com/products/product-materials/processor/mips-architecture/

Signed-off-by: Jia Liu <proljc@gmail.com>
---

Version History:
v12:
Addressed Aurelien&Richard's review comments:
- fix internal function mipsdsp_sat64_acc_sub_q63
- fix gen_mipsdsp_arith
- add more test cases

v11:
Addressed Johnson&Aurelien's review comments:
- change DSP r1 & r2 into microMIPS DSP r1 & r2 encodings in TODO file

Addressed Andreas's review comments:
- change subjects

v10:
Addressed Aurelien's review comments:
- remove useless return in mipsdsp_sat_abs and group mipsdsp_sat_abs_* by a macro
- using MIPSDSP_OVERFLOW to check overflow
- fix load
- use MIPSDSP_RETURN
- check for v1 and v2 being 0
- check for rs and rt being 0
- fix bit/manipulation instructions
- remove unnecessary arrays in compare-pick instructions
- fix 74kf's CP0_PRid

v9:
Addressed Aurelien's review comments:
- group translate actions by opcode
- group helpers using macro
- remove unused function not_word_value
- add absolute macro, overflow check macro, split/combine number macro
- undo delete bposge32/64 from micromips
- add return register 0 check

v8:
Addressed Aurelien's review comments:
- fix HFLAGS check, I hope it is right this time
- make a lot of code more clean
- fix branch instructions
- fix load instructions, I hope it is right this time
- fix bit instructions
- use a macro to deal CMP
- use 74kf instead of mips32dspr2

v7:
Addressed Aurelien's review comments:
- make hflags check for dsp, use check_dsp[r2]() instead of check_insn
- directly use cpu_dspctrl as the second argument in branch instructions
- factorizing some check_dsp() code one level
- remove unnecessary save_cpu_state() from load instructions
- resolve conflicts between MIPS DSP and loongson2e better
- make repl* more clean

v6:
Addressed Siarhei Siamashka's review comments:
- make internal function mipsdsp_mul_u8_u16 more clean

- fix MFHI MFLO MTHI MTLO, make mips64 linux run OK

v5:
Addressed Richard's review comments:
- bug shooting with --enanle-debug-tcg

- add check_insn for each DSP instructions
- MIPS64 ASE DSP support

v4:
Addressed Richard's review comments:
- split transalte.
- tested on i386 machine.
- delete all global env usage so that we don't need to include dyngen-exec.h.
- fix DEF_HELPER_FLAGS_N error.
- fix all ERRORS and WARNINGS found by ./scripts/checkpatch.pl.
- make sample if() code clearer.
- combine helper_cmpgu_cond_* and helper_cmpgdu_cond_*.
- fix bitrev.
- implement repl* and load with no helper.
- using TCG_COND_GE instead of TCG_COND_GT in OPC_BPOSGE32.

Thanks WeiRen for prereviewing and lots of suggestion.

v3:
Addressed Peter's review comments:
- split these changes into more patches.
- add "ULL" suffix for constants which are more than 32 bits wide.

Addressed WeiRen's review comments:
- split these changes into 12 patches.
- more suitable subject and description for every patch.

Addressed Richard's review comments:
- use DEF_HELPER_FLAGS_N instead of DEF_HELPER_N in some insns.
- put most DSP helpers into dsp_helper.c

- fix two testcases error.

v2:
Addressed Stefan's review comments:
- fixed coding style.
- changed acc into unsigned int form int and no initialization in translation.
- added return value in testcases.

v1:
- add MIPS ASE DSP Support.

Jia Liu (14):
  target-mips: Add ASE DSP internal functions
  target-mips: Add ASE DSP resources access check
  Use correct acc value to index cpu_HI/cpu_LO rather than using a fix
    number
  target-mips: Add ASE DSP branch instructions
  target-mips: Add ASE DSP load instructions
  target-mips: Add ASE DSP arithmetic instructions
  target-mips: Add ASE DSP GPR-based shift instructions
  target-mips: Add ASE DSP multiply instructions
  target-mips: Add ASE DSP bit/manipulation instructions
  target-mips: Add ASE DSP compare-pick instructions
  target-mips: Add ASE DSP accumulator instructions
  target-mips: Add ASE DSP processors
  target-mips: Add ASE DSP testcases
  target-mips: Change TODO file

 linux-user/main.c                              |    6 +
 target-mips/Makefile.objs                      |    2 +-
 target-mips/TODO                               |    3 +-
 target-mips/cpu.h                              |   23 +-
 target-mips/dsp_helper.c                       | 4033 ++++++++++++++++++++++++
 target-mips/helper.c                           |    3 +
 target-mips/helper.h                           |  349 ++
 target-mips/translate.c                        | 2965 ++++++++++++++++-
 target-mips/translate_init.c                   |   52 +
 tests/tcg/mips/mips32-dsp/Makefile             |  136 +
 tests/tcg/mips/mips32-dsp/absq_s_ph.c          |   31 +
 tests/tcg/mips/mips32-dsp/absq_s_w.c           |   37 +
 tests/tcg/mips/mips32-dsp/addq_ph.c            |   46 +
 tests/tcg/mips/mips32-dsp/addq_s_ph.c          |   69 +
 tests/tcg/mips/mips32-dsp/addq_s_w.c           |   44 +
 tests/tcg/mips/mips32-dsp/addsc.c              |   33 +
 tests/tcg/mips/mips32-dsp/addu_qb.c            |   35 +
 tests/tcg/mips/mips32-dsp/addu_s_qb.c          |   35 +
 tests/tcg/mips/mips32-dsp/addwc.c              |   49 +
 tests/tcg/mips/mips32-dsp/bitrev.c             |   20 +
 tests/tcg/mips/mips32-dsp/bposge32.c           |   44 +
 tests/tcg/mips/mips32-dsp/cmp_eq_ph.c          |   35 +
 tests/tcg/mips/mips32-dsp/cmp_le_ph.c          |   35 +
 tests/tcg/mips/mips32-dsp/cmp_lt_ph.c          |   35 +
 tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c        |   31 +
 tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c        |   31 +
 tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c        |   31 +
 tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c         |   35 +
 tests/tcg/mips/mips32-dsp/cmpu_le_qb.c         |   35 +
 tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c         |   35 +
 tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c        |   31 +
 tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c        |   77 +
 tests/tcg/mips/mips32-dsp/dpau_h_qbl.c         |   27 +
 tests/tcg/mips/mips32-dsp/dpau_h_qbr.c         |   27 +
 tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c        |   45 +
 tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c        |   55 +
 tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c         |   27 +
 tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c         |   27 +
 tests/tcg/mips/mips32-dsp/extp.c               |   44 +
 tests/tcg/mips/mips32-dsp/extpdp.c             |   46 +
 tests/tcg/mips/mips32-dsp/extpdpv.c            |   47 +
 tests/tcg/mips/mips32-dsp/extpv.c              |   45 +
 tests/tcg/mips/mips32-dsp/extr_r_w.c           |   48 +
 tests/tcg/mips/mips32-dsp/extr_rs_w.c          |   48 +
 tests/tcg/mips/mips32-dsp/extr_s_h.c           |   63 +
 tests/tcg/mips/mips32-dsp/extr_w.c             |   48 +
 tests/tcg/mips/mips32-dsp/extrv_r_w.c          |   54 +
 tests/tcg/mips/mips32-dsp/extrv_rs_w.c         |   52 +
 tests/tcg/mips/mips32-dsp/extrv_s_h.c          |   71 +
 tests/tcg/mips/mips32-dsp/extrv_w.c            |   54 +
 tests/tcg/mips/mips32-dsp/insv.c               |   23 +
 tests/tcg/mips/mips32-dsp/lbux.c               |   25 +
 tests/tcg/mips/mips32-dsp/lhx.c                |   25 +
 tests/tcg/mips/mips32-dsp/lwx.c                |   25 +
 tests/tcg/mips/mips32-dsp/madd.c               |   31 +
 tests/tcg/mips/mips32-dsp/maddu.c              |   31 +
 tests/tcg/mips/mips32-dsp/main.c               |    6 +
 tests/tcg/mips/mips32-dsp/maq_s_w_phl.c        |   55 +
 tests/tcg/mips/mips32-dsp/maq_s_w_phr.c        |   55 +
 tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c       |   55 +
 tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c       |   55 +
 tests/tcg/mips/mips32-dsp/mfhi.c               |   21 +
 tests/tcg/mips/mips32-dsp/mflo.c               |   21 +
 tests/tcg/mips/mips32-dsp/modsub.c             |   30 +
 tests/tcg/mips/mips32-dsp/msub.c               |   30 +
 tests/tcg/mips/mips32-dsp/msubu.c              |   30 +
 tests/tcg/mips/mips32-dsp/mthi.c               |   21 +
 tests/tcg/mips/mips32-dsp/mthlip.c             |   58 +
 tests/tcg/mips/mips32-dsp/mtlo.c               |   21 +
 tests/tcg/mips/mips32-dsp/muleq_s_w_phl.c      |   41 +
 tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c      |   40 +
 tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c     |   25 +
 tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c     |   25 +
 tests/tcg/mips/mips32-dsp/mulq_rs_ph.c         |   25 +
 tests/tcg/mips/mips32-dsp/mult.c               |   24 +
 tests/tcg/mips/mips32-dsp/multu.c              |   24 +
 tests/tcg/mips/mips32-dsp/packrl_ph.c          |   21 +
 tests/tcg/mips/mips32-dsp/pick_ph.c            |   49 +
 tests/tcg/mips/mips32-dsp/pick_qb.c            |   36 +
 tests/tcg/mips/mips32-dsp/preceq_w_phl.c       |   20 +
 tests/tcg/mips/mips32-dsp/preceq_w_phr.c       |   20 +
 tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c     |   20 +
 tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c    |   20 +
 tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c     |   20 +
 tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c    |   20 +
 tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c      |   20 +
 tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c     |   20 +
 tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c      |   20 +
 tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c     |   20 +
 tests/tcg/mips/mips32-dsp/precrq_ph_w.c        |   21 +
 tests/tcg/mips/mips32-dsp/precrq_qb_ph.c       |   21 +
 tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c     |   35 +
 tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c    |   24 +
 tests/tcg/mips/mips32-dsp/raddu_w_qb.c         |   20 +
 tests/tcg/mips/mips32-dsp/rddsp.c              |   54 +
 tests/tcg/mips/mips32-dsp/repl_ph.c            |   23 +
 tests/tcg/mips/mips32-dsp/repl_qb.c            |   16 +
 tests/tcg/mips/mips32-dsp/replv_ph.c           |   19 +
 tests/tcg/mips/mips32-dsp/replv_qb.c           |   19 +
 tests/tcg/mips/mips32-dsp/shilo.c              |   27 +
 tests/tcg/mips/mips32-dsp/shilov.c             |   29 +
 tests/tcg/mips/mips32-dsp/shll_ph.c            |   24 +
 tests/tcg/mips/mips32-dsp/shll_qb.c            |   36 +
 tests/tcg/mips/mips32-dsp/shll_s_ph.c          |   24 +
 tests/tcg/mips/mips32-dsp/shll_s_w.c           |   52 +
 tests/tcg/mips/mips32-dsp/shllv_ph.c           |   40 +
 tests/tcg/mips/mips32-dsp/shllv_qb.c           |   38 +
 tests/tcg/mips/mips32-dsp/shllv_s_ph.c         |   40 +
 tests/tcg/mips/mips32-dsp/shllv_s_w.c          |   40 +
 tests/tcg/mips/mips32-dsp/shra_ph.c            |   30 +
 tests/tcg/mips/mips32-dsp/shra_r_ph.c          |   30 +
 tests/tcg/mips/mips32-dsp/shra_r_w.c           |   30 +
 tests/tcg/mips/mips32-dsp/shrav_ph.c           |   32 +
 tests/tcg/mips/mips32-dsp/shrav_r_ph.c         |   32 +
 tests/tcg/mips/mips32-dsp/shrav_r_w.c          |   32 +
 tests/tcg/mips/mips32-dsp/shrl_qb.c            |   31 +
 tests/tcg/mips/mips32-dsp/shrlv_qb.c           |   32 +
 tests/tcg/mips/mips32-dsp/subq_ph.c            |   40 +
 tests/tcg/mips/mips32-dsp/subq_s_ph.c          |   40 +
 tests/tcg/mips/mips32-dsp/subq_s_w.c           |   58 +
 tests/tcg/mips/mips32-dsp/subu_qb.c            |   25 +
 tests/tcg/mips/mips32-dsp/subu_s_qb.c          |   25 +
 tests/tcg/mips/mips32-dsp/wrdsp.c              |   54 +
 tests/tcg/mips/mips32-dspr2/Makefile           |   71 +
 tests/tcg/mips/mips32-dspr2/absq_s_qb.c        |   35 +
 tests/tcg/mips/mips32-dspr2/addqh_ph.c         |   30 +
 tests/tcg/mips/mips32-dspr2/addqh_r_ph.c       |   30 +
 tests/tcg/mips/mips32-dspr2/addqh_r_w.c        |   34 +
 tests/tcg/mips/mips32-dspr2/addqh_w.c          |   34 +
 tests/tcg/mips/mips32-dspr2/addu_ph.c          |   33 +
 tests/tcg/mips/mips32-dspr2/addu_s_ph.c        |   33 +
 tests/tcg/mips/mips32-dspr2/adduh_qb.c         |   30 +
 tests/tcg/mips/mips32-dspr2/adduh_r_qb.c       |   30 +
 tests/tcg/mips/mips32-dspr2/append.c           |   30 +
 tests/tcg/mips/mips32-dspr2/balign.c           |   30 +
 tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c     |   37 +
 tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c     |   37 +
 tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c     |   37 +
 tests/tcg/mips/mips32-dspr2/dpa_w_ph.c         |   44 +
 tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c     |   79 +
 tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c    |   53 +
 tests/tcg/mips/mips32-dspr2/dpax_w_ph.c        |   27 +
 tests/tcg/mips/mips32-dspr2/dps_w_ph.c         |   27 +
 tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c     |   54 +
 tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c    |   53 +
 tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c        |   27 +
 tests/tcg/mips/mips32-dspr2/mul_ph.c           |   47 +
 tests/tcg/mips/mips32-dspr2/mul_s_ph.c         |   62 +
 tests/tcg/mips/mips32-dspr2/mulq_rs_w.c        |   36 +
 tests/tcg/mips/mips32-dspr2/mulq_s_ph.c        |   25 +
 tests/tcg/mips/mips32-dspr2/mulq_s_w.c         |   36 +
 tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c       |   29 +
 tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c    |   29 +
 tests/tcg/mips/mips32-dspr2/precr_qb_ph.c      |   21 +
 tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c   |   32 +
 tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c |   32 +
 tests/tcg/mips/mips32-dspr2/prepend.c          |   30 +
 tests/tcg/mips/mips32-dspr2/shra_qb.c          |   30 +
 tests/tcg/mips/mips32-dspr2/shra_r_qb.c        |   30 +
 tests/tcg/mips/mips32-dspr2/shrav_qb.c         |   32 +
 tests/tcg/mips/mips32-dspr2/shrav_r_qb.c       |   32 +
 tests/tcg/mips/mips32-dspr2/shrl_ph.c          |   20 +
 tests/tcg/mips/mips32-dspr2/shrlv_ph.c         |   21 +
 tests/tcg/mips/mips32-dspr2/subqh_ph.c         |   21 +
 tests/tcg/mips/mips32-dspr2/subqh_r_ph.c       |   21 +
 tests/tcg/mips/mips32-dspr2/subqh_r_w.c        |   21 +
 tests/tcg/mips/mips32-dspr2/subqh_w.c          |   21 +
 tests/tcg/mips/mips32-dspr2/subu_ph.c          |   40 +
 tests/tcg/mips/mips32-dspr2/subu_s_ph.c        |   25 +
 tests/tcg/mips/mips32-dspr2/subuh_qb.c         |   21 +
 tests/tcg/mips/mips32-dspr2/subuh_r_qb.c       |   32 +
 tests/tcg/mips/mips64-dsp/Makefile             |  306 ++
 tests/tcg/mips/mips64-dsp/absq_s_ob.c          |   63 +
 tests/tcg/mips/mips64-dsp/absq_s_ph.c          |   37 +
 tests/tcg/mips/mips64-dsp/absq_s_pw.c          |   66 +
 tests/tcg/mips/mips64-dsp/absq_s_qh.c          |   40 +
 tests/tcg/mips/mips64-dsp/absq_s_w.c           |   48 +
 tests/tcg/mips/mips64-dsp/addq_ph.c            |   57 +
 tests/tcg/mips/mips64-dsp/addq_pw.c            |   46 +
 tests/tcg/mips/mips64-dsp/addq_qh.c            |   28 +
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 tests/tcg/mips/mips64-dspr2/dpa_w_ph.c         |   47 +
 tests/tcg/mips/mips64-dspr2/dpa_w_qh.c         |   56 +
 tests/tcg/mips/mips64-dspr2/dpaqx_s_w_ph.c     |   97 +
 tests/tcg/mips/mips64-dspr2/dpaqx_sa_w_ph.c    |   54 +
 tests/tcg/mips/mips64-dspr2/dpax_w_ph.c        |   32 +
 tests/tcg/mips/mips64-dspr2/dps_w_ph.c         |   28 +
 tests/tcg/mips/mips64-dspr2/dps_w_qh.c         |   55 +
 tests/tcg/mips/mips64-dspr2/dpsqx_s_w_ph.c     |   55 +
 tests/tcg/mips/mips64-dspr2/dpsqx_sa_w_ph.c    |   53 +
 tests/tcg/mips/mips64-dspr2/dpsx_w_ph.c        |   28 +
 tests/tcg/mips/mips64-dspr2/head.S             |   16 +
 tests/tcg/mips/mips64-dspr2/io.h               |   22 +
 tests/tcg/mips/mips64-dspr2/mips_boot.lds      |   31 +
 tests/tcg/mips/mips64-dspr2/mul_ph.c           |   50 +
 tests/tcg/mips/mips64-dspr2/mul_s_ph.c         |   67 +
 tests/tcg/mips/mips64-dspr2/mulq_rs_w.c        |   40 +
 tests/tcg/mips/mips64-dspr2/mulq_s_ph.c        |   26 +
 tests/tcg/mips/mips64-dspr2/mulq_s_w.c         |   40 +
 tests/tcg/mips/mips64-dspr2/mulsa_w_ph.c       |   30 +
 tests/tcg/mips/mips64-dspr2/mulsaq_s_w_ph.c    |   30 +
 tests/tcg/mips/mips64-dspr2/precr_qb_ph.c      |   23 +
 tests/tcg/mips/mips64-dspr2/precr_sra_ph_w.c   |   37 +
 tests/tcg/mips/mips64-dspr2/precr_sra_r_ph_w.c |   37 +
 tests/tcg/mips/mips64-dspr2/prepend.c          |   35 +
 tests/tcg/mips/mips64-dspr2/printf.c           |  266 ++
 tests/tcg/mips/mips64-dspr2/shra_qb.c          |   35 +
 tests/tcg/mips/mips64-dspr2/shra_r_qb.c        |   35 +
 tests/tcg/mips/mips64-dspr2/shrav_ob.c         |   22 +
 tests/tcg/mips/mips64-dspr2/shrav_qb.c         |   37 +
 tests/tcg/mips/mips64-dspr2/shrav_r_ob.c       |   22 +
 tests/tcg/mips/mips64-dspr2/shrav_r_qb.c       |   37 +
 tests/tcg/mips/mips64-dspr2/shrl_ph.c          |   22 +
 tests/tcg/mips/mips64-dspr2/shrlv_ph.c         |   23 +
 tests/tcg/mips/mips64-dspr2/subqh_ph.c         |   23 +
 tests/tcg/mips/mips64-dspr2/subqh_r_ph.c       |   23 +
 tests/tcg/mips/mips64-dspr2/subqh_r_w.c        |   23 +
 tests/tcg/mips/mips64-dspr2/subqh_w.c          |   23 +
 tests/tcg/mips/mips64-dspr2/subu_ph.c          |   26 +
 tests/tcg/mips/mips64-dspr2/subu_qh.c          |   24 +
 tests/tcg/mips/mips64-dspr2/subu_s_ph.c        |   25 +
 tests/tcg/mips/mips64-dspr2/subu_s_qh.c        |   42 +
 tests/tcg/mips/mips64-dspr2/subuh_ob.c         |   36 +
 tests/tcg/mips/mips64-dspr2/subuh_qb.c         |   23 +
 tests/tcg/mips/mips64-dspr2/subuh_r_ob.c       |   23 +
 tests/tcg/mips/mips64-dspr2/subuh_r_qb.c       |   37 +
 496 files changed, 26481 insertions(+), 106 deletions(-)
 create mode 100644 target-mips/dsp_helper.c
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 create mode 100644 tests/tcg/mips/mips64-dspr2/subuh_r_qb.c

-- 
1.7.10.2 (Apple Git-33)

[Qemu-devel] [PATCH v12 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Jia Liu]

Add MIPS ASE DSP Bit/Manipulation instructions.

Signed-off-by: Jia Liu <proljc@gmail.com>
---
 target-mips/dsp_helper.c |   55 ++++++++++
 target-mips/helper.h     |    7 ++
 target-mips/translate.c  |  249 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 311 insertions(+)

diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 86c27ec..919ff29 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3112,6 +3112,61 @@ DM_OPERATE(dmsubu, mul_u32_u32, 0, 0);
 #undef DM_OPERATE
 #endif
 
+/** DSP Bit/Manipulation Sub-class insns **/
+target_ulong helper_bitrev(target_ulong rt)
+{
+    int32_t temp;
+    uint32_t rd;
+    int i;
+
+    temp = rt & MIPSDSP_LO;
+    rd = 0;
+    for (i = 0; i < 16; i++) {
+        rd = (rd << 1) | (temp & 1);
+        temp = temp >> 1;
+    }
+
+    return (target_ulong)rd;
+}
+
+#define BIT_INSV(name, posfilter, sizefilter, ret_type)         \
+target_ulong helper_##name(CPUMIPSState *env, target_ulong rs,  \
+                           target_ulong rt)                     \
+{                                                               \
+    uint32_t pos, size, msb, lsb;                               \
+    target_ulong filter;                                        \
+    target_ulong temp, temprs, temprt;                          \
+    target_ulong dspc;                                          \
+                                                                \
+    dspc = env->active_tc.DSPControl;                           \
+                                                                \
+    pos  = dspc & posfilter;                                    \
+    size = (dspc >> 7) & sizefilter;                            \
+                                                                \
+    msb  = pos + size - 1;                                      \
+    lsb  = pos;                                                 \
+                                                                \
+    if (lsb > msb || (msb > TARGET_LONG_BITS)) {                \
+        return rt;                                              \
+    }                                                           \
+                                                                \
+    filter = ((int32_t)0x01 << size) - 1;                       \
+    filter = filter << pos;                                     \
+    temprs = rs & filter;                                       \
+    temprt = rt & ~filter;                                      \
+    temp = temprs | temprt;                                     \
+                                                                \
+    return (target_long)(ret_type)temp;                         \
+}
+
+BIT_INSV(insv, 0x1F, 0x1F, int32_t);
+#ifdef TARGET_MIPS64
+BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
+#endif
+
+#undef BIT_INSV
+
+
 #undef MIPSDSP_LHI
 #undef MIPSDSP_LLO
 #undef MIPSDSP_HI
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 6a6ca99..31475a2 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -617,4 +617,11 @@ DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env)
 DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env)
 #endif
 
+/* DSP Bit/Manipulation Sub-class insns */
+DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
+DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl)
+#if defined(TARGET_MIPS64)
+DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl);
+#endif
+
 #include "def-helper.h"
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7c90941..63109f4 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -343,6 +343,11 @@ enum {
 #if defined(TARGET_MIPS64)
     OPC_DPAQ_W_QH_DSP  = 0x34 | OPC_SPECIAL3,
 #endif
+    /* DSP Bit/Manipulation Sub-class */
+    OPC_INSV_DSP       = 0x0C | OPC_SPECIAL3,
+#if defined(TARGET_MIPS64)
+    OPC_DINSV_DSP      = 0x0D | OPC_SPECIAL3,
+#endif
 };
 
 /* BSHFL opcodes */
@@ -450,6 +455,12 @@ enum {
     OPC_PRECEU_PH_QBR   = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
     OPC_PRECEU_PH_QBLA  = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
     OPC_PRECEU_PH_QBRA  = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
+    /* DSP Bit/Manipulation Sub-class */
+    OPC_BITREV          = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
+    OPC_REPL_QB         = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
+    OPC_REPLV_QB        = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
+    OPC_REPL_PH         = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
+    OPC_REPLV_PH        = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
 };
 
 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
@@ -518,6 +529,12 @@ enum {
     OPC_MULSA_W_PH    = (0x02 << 6) | OPC_DPA_W_PH_DSP,
 };
 
+#define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+    /* DSP Bit/Manipulation Sub-class */
+    OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
+};
+
 #if defined(TARGET_MIPS64)
 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 enum {
@@ -539,6 +556,13 @@ enum {
     OPC_ABSQ_S_OB       = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
     OPC_ABSQ_S_PW       = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
     OPC_ABSQ_S_QH       = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
+    /* DSP Bit/Manipulation Sub-class */
+    OPC_REPL_OB         = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
+    OPC_REPL_PW         = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
+    OPC_REPL_QH         = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
+    OPC_REPLV_OB        = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
+    OPC_REPLV_PW        = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
+    OPC_REPLV_QH        = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
 };
 #endif
 
@@ -592,6 +616,14 @@ enum {
 #endif
 
 #if defined(TARGET_MIPS64)
+#define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+    /* DSP Bit/Manipulation Sub-class */
+    OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
+};
+#endif
+
+#if defined(TARGET_MIPS64)
 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
 enum {
     /* MIPS DSP Multiply Sub-class insns */
@@ -13598,6 +13630,149 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
 
 }
 
+static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx,
+                                uint32_t op1, uint32_t op2,
+                                int ret, int val)
+{
+    const char *opn = "mipsdsp Bit/ Manipulation";
+    int16_t imm;
+    TCGv t0;
+    TCGv val_t;
+
+    if (ret == 0) {
+        /* Treat as NOP. */
+        MIPS_DEBUG("NOP");
+        return;
+    }
+
+    t0 = tcg_temp_new();
+    val_t = tcg_temp_new();
+    gen_load_gpr(val_t, val);
+
+    switch (op1) {
+    case OPC_ABSQ_S_PH_DSP:
+        switch (op2) {
+        case OPC_BITREV:
+            check_dsp(ctx);
+            gen_helper_bitrev(cpu_gpr[ret], val_t);
+            break;
+        case OPC_REPL_QB:
+            check_dsp(ctx);
+            {
+                target_long result;
+                imm = (ctx->opcode >> 16) & 0xFF;
+                result = (uint32_t)imm << 24 |
+                         (uint32_t)imm << 16 |
+                         (uint32_t)imm << 8  |
+                         (uint32_t)imm;
+                result = (int32_t)result;
+                tcg_gen_movi_tl(cpu_gpr[ret], result);
+            }
+            break;
+        case OPC_REPLV_QB:
+            check_dsp(ctx);
+            tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+            break;
+        case OPC_REPL_PH:
+            check_dsp(ctx);
+            {
+                imm = (ctx->opcode >> 16) & 0x03FF;
+                tcg_gen_movi_tl(cpu_gpr[ret], \
+                                (target_long)((int32_t)imm << 16 | \
+                                (uint32_t)(uint16_t)imm));
+            }
+            break;
+        case OPC_REPLV_PH:
+            check_dsp(ctx);
+            tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
+            break;
+        }
+        break;
+#ifdef TARGET_MIPS64
+    case OPC_ABSQ_S_QH_DSP:
+        switch (op2) {
+        case OPC_REPL_OB:
+            check_dsp(ctx);
+            {
+                target_long temp;
+
+                imm = (ctx->opcode >> 16) & 0xFF;
+                temp = ((uint64_t)imm << 8) | (uint64_t)imm;
+                temp = (temp << 16) | temp;
+                temp = (temp << 32) | temp;
+                tcg_gen_movi_tl(cpu_gpr[ret], temp);
+                break;
+            }
+        case OPC_REPL_PW:
+            check_dsp(ctx);
+            {
+                target_long temp;
+
+                imm = (ctx->opcode >> 16) & 0x03FF;
+                imm = (int16_t)(imm << 6) >> 6;
+                temp = ((target_long)imm << 32) \
+                       | ((target_long)imm & 0xFFFFFFFF);
+                tcg_gen_movi_tl(cpu_gpr[ret], temp);
+                break;
+            }
+        case OPC_REPL_QH:
+            check_dsp(ctx);
+            {
+                target_long temp;
+
+                imm = (ctx->opcode >> 16) & 0x03FF;
+                imm = (int16_t)(imm << 6) >> 6;
+
+                temp = ((uint64_t)(uint16_t)imm << 48) |
+                       ((uint64_t)(uint16_t)imm << 32) |
+                       ((uint64_t)(uint16_t)imm << 16) |
+                       (uint64_t)(uint16_t)imm;
+                tcg_gen_movi_tl(cpu_gpr[ret], temp);
+                break;
+            }
+        case OPC_REPLV_OB:
+            check_dsp(ctx);
+            tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            break;
+        case OPC_REPLV_PW:
+            check_dsp(ctx);
+            tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            break;
+        case OPC_REPLV_QH:
+            check_dsp(ctx);
+            tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
+            tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
+            break;
+        }
+        break;
+#endif
+    }
+    tcg_temp_free(t0);
+    tcg_temp_free(val_t);
+
+    (void)opn; /* avoid a compiler warning */
+    MIPS_DEBUG("%s", opn);
+}
+
 /* End MIPSDSP functions. */
 
 static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
@@ -14024,6 +14199,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
             case OPC_PRECEU_PH_QBRA:
                 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
                 break;
+            case OPC_BITREV:
+            case OPC_REPL_QB:
+            case OPC_REPLV_QB:
+            case OPC_REPL_PH:
+            case OPC_REPLV_PH:
+                gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt);
+                break;
             default:
                 MIPS_INVAL("MASK ABSQ_S.PH");
                 generate_exception(ctx, EXCP_RI);
@@ -14124,6 +14306,37 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
                 break;
             }
             break;
+        case OPC_INSV_DSP:
+            op2 = MASK_INSV(ctx->opcode);
+            switch (op2) {
+            case OPC_INSV:
+                check_dsp(ctx);
+                {
+                    TCGv t0, t1;
+
+                    if (rt == 0) {
+                        MIPS_DEBUG("NOP");
+                        break;
+                    }
+
+                    t0 = tcg_temp_new();
+                    t1 = tcg_temp_new();
+
+                    gen_load_gpr(t0, rt);
+                    gen_load_gpr(t1, rs);
+
+                    gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0);
+
+                    tcg_temp_free(t0);
+                    tcg_temp_free(t1);
+                    break;
+                }
+            default:            /* Invalid */
+                MIPS_INVAL("MASK INSV");
+                generate_exception(ctx, EXCP_RI);
+                break;
+            }
+            break;
 #if defined(TARGET_MIPS64)
         case OPC_DEXTM ... OPC_DEXT:
         case OPC_DINSM ... OPC_DINS:
@@ -14165,6 +14378,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
             case OPC_ABSQ_S_QH:
                 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
                 break;
+            case OPC_REPL_OB:
+            case OPC_REPL_PW:
+            case OPC_REPL_QH:
+            case OPC_REPLV_OB:
+            case OPC_REPLV_PW:
+            case OPC_REPLV_QH:
+                gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt);
+                break;
             default:            /* Invalid */
                 MIPS_INVAL("MASK ABSQ_S.QH");
                 generate_exception(ctx, EXCP_RI);
@@ -14271,6 +14492,34 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch)
                 break;
             }
             break;
+        case OPC_DINSV_DSP:
+            op2 = MASK_INSV(ctx->opcode);
+            switch (op2) {
+            case OPC_DINSV:
+                {
+                    TCGv t0, t1;
+
+                    if (rt == 0) {
+                        MIPS_DEBUG("NOP");
+                        break;
+                    }
+                    check_dsp(ctx);
+
+                    t0 = tcg_temp_new();
+                    t1 = tcg_temp_new();
+
+                    gen_load_gpr(t0, rt);
+                    gen_load_gpr(t1, rs);
+
+                    gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0);
+                    break;
+                }
+            default:            /* Invalid */
+                MIPS_INVAL("MASK DINSV");
+                generate_exception(ctx, EXCP_RI);
+                break;
+            }
+            break;
         case OPC_SHLL_OB_DSP:
             gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
             break;
-- 
1.7.10.2 (Apple Git-33)