From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35058) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTao0-0002aA-U3 for qemu-devel@nongnu.org; Wed, 31 Oct 2012 12:06:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TTanq-0005my-Dz for qemu-devel@nongnu.org; Wed, 31 Oct 2012 12:06:12 -0400 Received: from cantor2.suse.de ([195.135.220.15]:57655 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TTanq-0005lo-01 for qemu-devel@nongnu.org; Wed, 31 Oct 2012 12:06:02 -0400 Message-ID: <50914C65.8040303@suse.de> Date: Wed, 31 Oct 2012 17:05:57 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1351596522-8142-1-git-send-email-kraxel@redhat.com> <1351596522-8142-4-git-send-email-kraxel@redhat.com> In-Reply-To: <1351596522-8142-4-git-send-email-kraxel@redhat.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RfC PATCH 3/5] usb/ehci: seperate out PCIisms List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: peter.crosthwaite@xilinx.com, qemu-devel@nongnu.org Am 30.10.2012 12:28, schrieb Gerd Hoffmann: > From: Peter Crosthwaite >=20 > Seperate the PCI stuff from the EHCI components. Extracted the PCIDevic= e > out into a new wrapper struct to make EHCIState non-PCI-specific. Seper= ated > tho non PCI init component out into a seperate "common" init function. >=20 > Signed-off-by: Peter Crosthwaite > Signed-off-by: Gerd Hoffmann > --- > hw/usb/hcd-ehci.c | 124 +++++++++++++++++++++++++++++++--------------= -------- > 1 files changed, 72 insertions(+), 52 deletions(-) >=20 > diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c > index 28890b5..59580fc 100644 > --- a/hw/usb/hcd-ehci.c > +++ b/hw/usb/hcd-ehci.c > @@ -385,7 +385,6 @@ struct EHCIQueue { > typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; > =20 > struct EHCIState { > - PCIDevice dev; > USBBus bus; > qemu_irq irq; > MemoryRegion mem; > @@ -447,6 +446,11 @@ struct EHCIState { > bool int_req_by_async; > }; > =20 > +typedef struct EHCIPCIState { > + PCIDevice pcidev; > + EHCIState ehci; > +} EHCIPCIState; > + > #define SET_LAST_RUN_CLOCK(s) \ > (s)->last_run_ns =3D qemu_get_clock_ns(vm_clock); > =20 > @@ -2553,7 +2557,7 @@ static const MemoryRegionOps ehci_mmio_port_ops =3D= { > .endianness =3D DEVICE_LITTLE_ENDIAN, > }; > =20 > -static int usb_ehci_initfn(PCIDevice *dev); > +static int usb_ehci_pci_initfn(PCIDevice *dev); > =20 > static USBPortOps ehci_port_ops =3D { > .attach =3D ehci_attach, > @@ -2614,12 +2618,11 @@ static void usb_ehci_vm_state_change(void *opaq= ue, int running, RunState state) > } > =20 > static const VMStateDescription vmstate_ehci =3D { > - .name =3D "ehci", > + .name =3D "ehci-core", > .version_id =3D 2, > .minimum_version_id =3D 1, > .post_load =3D usb_ehci_post_load, > .fields =3D (VMStateField[]) { > - VMSTATE_PCI_DEVICE(dev, EHCIState), > /* mmio registers */ > VMSTATE_UINT32(usbcmd, EHCIState), > VMSTATE_UINT32(usbsts, EHCIState), > @@ -2650,8 +2653,19 @@ static const VMStateDescription vmstate_ehci =3D= { > } > }; > =20 > -static Property ehci_properties[] =3D { > - DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), > +static const VMStateDescription vmstate_ehci_pci =3D { > + .name =3D "ehci", > + .version_id =3D 2, > + .minimum_version_id =3D 1, > + .post_load =3D usb_ehci_post_load, > + .fields =3D (VMStateField[]) { > + VMSTATE_PCI_DEVICE(pcidev, EHCIPCIState), > + VMSTATE_STRUCT(ehci, EHCIPCIState, 2, vmstate_ehci, EHCIState)= , > + } > +}; > + > +static Property ehci_pci_properties[] =3D { > + DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128)= , > DEFINE_PROP_END_OF_LIST(), > }; > =20 > @@ -2660,13 +2674,13 @@ static void ehci_class_init(ObjectClass *klass,= void *data) > DeviceClass *dc =3D DEVICE_CLASS(klass); > PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); > =20 > - k->init =3D usb_ehci_initfn; > + k->init =3D usb_ehci_pci_initfn; > k->vendor_id =3D PCI_VENDOR_ID_INTEL; > k->device_id =3D PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ > k->revision =3D 0x10; > k->class_id =3D PCI_CLASS_SERIAL_USB; > dc->vmsd =3D &vmstate_ehci; > - dc->props =3D ehci_properties; > + dc->props =3D ehci_pci_properties; > } > =20 > static TypeInfo ehci_info =3D { > @@ -2681,13 +2695,13 @@ static void ich9_ehci_class_init(ObjectClass *k= lass, void *data) > DeviceClass *dc =3D DEVICE_CLASS(klass); > PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); > =20 > - k->init =3D usb_ehci_initfn; > + k->init =3D usb_ehci_pci_initfn; > k->vendor_id =3D PCI_VENDOR_ID_INTEL; > k->device_id =3D PCI_DEVICE_ID_INTEL_82801I_EHCI1; > k->revision =3D 0x03; > k->class_id =3D PCI_CLASS_SERIAL_USB; > dc->vmsd =3D &vmstate_ehci; > - dc->props =3D ehci_properties; > + dc->props =3D ehci_pci_properties; > } > =20 > static TypeInfo ich9_ehci_info =3D { > @@ -2697,44 +2711,10 @@ static TypeInfo ich9_ehci_info =3D { > .class_init =3D ich9_ehci_class_init, > }; > =20 > -static int usb_ehci_initfn(PCIDevice *dev) > +static void usb_ehci_initfn(EHCIState *s, DeviceState *dev) > { > - EHCIState *s =3D DO_UPCAST(EHCIState, dev, dev); > - uint8_t *pci_conf =3D s->dev.config; > int i; > =20 > - pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); > - > - /* capabilities pointer */ > - pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); > - //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); > - > - pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D = */ > - pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); > - pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); > - > - // pci_conf[0x50] =3D 0x01; // power management caps > - > - pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release numbe= r (2.1.4) > - pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (= 2.1.5) > - pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (= 2.1.6) > - > - pci_conf[0x64] =3D 0x00; > - pci_conf[0x65] =3D 0x00; > - pci_conf[0x66] =3D 0x00; > - pci_conf[0x67] =3D 0x00; > - pci_conf[0x68] =3D 0x01; > - pci_conf[0x69] =3D 0x00; > - pci_conf[0x6a] =3D 0x00; > - pci_conf[0x6b] =3D 0x00; // USBLEGSUP > - pci_conf[0x6c] =3D 0x00; > - pci_conf[0x6d] =3D 0x00; > - pci_conf[0x6e] =3D 0x00; > - pci_conf[0x6f] =3D 0xc0; // USBLEFCTLSTS > - > - s->capsbase =3D 0x00; > - s->opregbase =3D 0x20; > - > /* 2.2 host controller interface version */ > s->caps[0x00] =3D (uint8_t)(s->opregbase - s->capsbase); > s->caps[0x01] =3D 0x00; > @@ -2745,15 +2725,10 @@ static int usb_ehci_initfn(PCIDevice *dev) > s->caps[0x06] =3D 0x00; > s->caps[0x07] =3D 0x00; > s->caps[0x08] =3D 0x80; /* We can cache whole frame, no 64-= bit */ > - s->caps[0x09] =3D 0x68; /* EECP */ > s->caps[0x0a] =3D 0x00; > s->caps[0x0b] =3D 0x00; > =20 > - s->irq =3D s->dev.irq[3]; > - > - s->dma =3D pci_dma_context(dev); > - > - usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); > + usb_bus_new(&s->bus, &ehci_bus_ops, dev); > for(i =3D 0; i < NB_PORTS; i++) { > usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, > USB_SPEED_MASK_HIGH); > @@ -2781,8 +2756,53 @@ static int usb_ehci_initfn(PCIDevice *dev) > memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); > memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, > &s->mem_ports); > +} > + > +static int usb_ehci_pci_initfn(PCIDevice *dev) > +{ > + EHCIPCIState *i =3D DO_UPCAST(EHCIPCIState, pcidev, dev); Same as discussed for Peter's patchset, this should be using a QOM cast macro and may need an abstract base type if there is no unique type matching EHCIPCIState struct. Should I send you a follow-up to squash if this is the approach we are going to take? Andreas > + EHCIState *s =3D &i->ehci; > + uint8_t *pci_conf =3D dev->config; > + > + pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); > + > + /* capabilities pointer */ > + pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); > + /* pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); */ > + > + pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D = */ > + pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); > + pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); > + > + /* pci_conf[0x50] =3D 0x01; *//* power management caps */ > + > + pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); /* release # (2.= 1.4) */ > + pci_set_byte(&pci_conf[0x61], 0x20); /* frame length adjustment (= 2.1.5) */ > + pci_set_word(&pci_conf[0x62], 0x00); /* port wake up capability (= 2.1.6) */ > + > + pci_conf[0x64] =3D 0x00; > + pci_conf[0x65] =3D 0x00; > + pci_conf[0x66] =3D 0x00; > + pci_conf[0x67] =3D 0x00; > + pci_conf[0x68] =3D 0x01; > + pci_conf[0x69] =3D 0x00; > + pci_conf[0x6a] =3D 0x00; > + pci_conf[0x6b] =3D 0x00; /* USBLEGSUP */ > + pci_conf[0x6c] =3D 0x00; > + pci_conf[0x6d] =3D 0x00; > + pci_conf[0x6e] =3D 0x00; > + pci_conf[0x6f] =3D 0xc0; /* USBLEFCTLSTS */ > + > + s->caps[0x09] =3D 0x68; /* EECP */ > + > + s->irq =3D dev->irq[3]; > + s->dma =3D pci_dma_context(dev); > + > + s->capsbase =3D 0x00; > + s->opregbase =3D 0x20; > =20 > - pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->me= m); > + usb_ehci_initfn(s, DEVICE(dev)); > + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); > =20 > return 0; > } >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg