From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:53861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TZ9Oz-0004Y3-M1 for qemu-devel@nongnu.org; Thu, 15 Nov 2012 19:03:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TZ9Ow-0001mW-Jp for qemu-devel@nongnu.org; Thu, 15 Nov 2012 19:03:21 -0500 Received: from mail-pb0-f45.google.com ([209.85.160.45]:41854) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TZ9Ow-0001m4-E4 for qemu-devel@nongnu.org; Thu, 15 Nov 2012 19:03:18 -0500 Received: by mail-pb0-f45.google.com with SMTP id mc8so1467701pbc.4 for ; Thu, 15 Nov 2012 16:03:17 -0800 (PST) Sender: Richard Henderson Message-ID: <50A582C2.5090908@twiddle.net> Date: Thu, 15 Nov 2012 16:03:14 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1914486608.9887816.1352801368641.JavaMail.root@redhat.com> <50A368CD.1080002@redhat.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v6 1/8] atomic: introduce atomic operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: liu ping fan Cc: Peter Maydell , Stefan Hajnoczi , Marcelo Tosatti , qemu-devel@nongnu.org, Avi Kivity , Anthony Liguori , Jan Kiszka , Paolo Bonzini On 2012-11-14 23:47, liu ping fan wrote: > Probably I made a mistake here, in vhost, log = > __sync_fetch_and_and(from, 0) is used to fetch 64bits atomically in > the case 32bits qemu running on 64bits linux. Right? But how can > we read 32bits twice in atomic? Seem that no instruction like "_lock > xchg" for this ops. So I guess _sync_fetch_and_and() based on > something like spinlock. ... or for gcc 4.7 and later, log = __atomic_load_n(from, memory_model) For i386, we will not perform 2 32-bit reads of course. Paulo suggests using cmpxchg8b, but that's a tad slow. Instead we'll perform a 64-bit read into either the fpu or the sse units, and from there copy the data wherever it's needed. Such 64-bit aligned reads are guaranteed to be atomic for i586 (pentium) and later. For other 32-bit architectures other possibilities exist. Recent arm can use its ldrexd insn. Many of the 32-bit linux architectures have special kernel entry points or schemes to perform atomic operations. These are generally based on the assumption of a single-processor system, and are arranged to either disable interrupts or notice that no interrupt occurred, while executing a code region. As an ultimate fallback, yes we would use locks. But none of the host architectures that QEMU supports needs to do so. r~