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Date: Sun, 02 Dec 2012 01:27:39 +0400
From: Igor Mitsyanko <i.mitsyanko@gmail.com>
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References: <1354208577-8935-1-git-send-email-peter.maydell@linaro.org>
	<1354208577-8935-3-git-send-email-peter.maydell@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH 2/3] hw/arm_gic: Fix comparison with
	priority mask register
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Igor Mitsyanko <i.mitsyanko@samsung.com>, Mark Langsdorf <mark.langsdorf@calxeda.com>, Evgeny Voevodin <e.voevodin@samsung.com>, patches@linaro.org, Marc Zyngier <marc.zyngier@arm.com>, qemu-devel@nongnu.org, Dmitry Solodkiy <d.solodkiy@samsung.com>, Maksim Kozlov <m.kozlov@samsung.com>, kvmarm@lists.cs.columbia.edu

On 11/29/2012 9:02 PM, Peter Maydell wrote:
> The GIC spec states that only interrupts with higher priority
> than the value in the GICC_PMR priority mask register are
> passed through to the processor. We were incorrectly allowing
> through interrupts with a priority equal to the specified
> value: correct the comparison operation to match the spec.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   hw/arm_gic.c |    2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index f9e423f..672d539 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -73,7 +73,7 @@ void gic_update(GICState *s)
>               }
>           }
>           level = 0;
> -        if (best_prio <= s->priority_mask[cpu]) {
> +        if (best_prio < s->priority_mask[cpu]) {
>               s->current_pending[cpu] = best_irq;
>               if (best_prio < s->running_priority[cpu]) {
>                   DPRINTF("Raised pending IRQ %d\n", best_irq);
>


Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>