From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47225) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TeubQ-0005G5-GU for qemu-devel@nongnu.org; Sat, 01 Dec 2012 16:28:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TeubP-0006Qq-Gq for qemu-devel@nongnu.org; Sat, 01 Dec 2012 16:28:00 -0500 Received: from mail-la0-f45.google.com ([209.85.215.45]:54522) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TeubP-0006AB-8I for qemu-devel@nongnu.org; Sat, 01 Dec 2012 16:27:59 -0500 Received: by mail-la0-f45.google.com with SMTP id p9so1161967laa.4 for ; Sat, 01 Dec 2012 13:27:58 -0800 (PST) Message-ID: <50BA765E.9070001@gmail.com> Date: Sun, 02 Dec 2012 01:27:58 +0400 From: Igor Mitsyanko MIME-Version: 1.0 References: <1354208577-8935-1-git-send-email-peter.maydell@linaro.org> <1354208577-8935-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1354208577-8935-4-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/3] hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Igor Mitsyanko , Mark Langsdorf , Evgeny Voevodin , patches@linaro.org, Marc Zyngier , qemu-devel@nongnu.org, Dmitry Solodkiy , Maksim Kozlov , kvmarm@lists.cs.columbia.edu On 11/29/2012 9:02 PM, Peter Maydell wrote: > The GIC architecture specification for v1 and v2 GICs (as found > on the Cortex-A9 and newer) states that the GICC_PMR reset value > is zero; this differs from the 0xf0 reset value used on 11MPCore. > The NVIC is different again in not having a CPU interface; since > we share the GIC code we must force the priority mask field to > allow through all interrupts. > > Signed-off-by: Peter Maydell > --- > hw/arm_gic_common.c | 6 +++++- > hw/armv7m_nvic.c | 4 +++- > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c > index 8369309..73ae331 100644 > --- a/hw/arm_gic_common.c > +++ b/hw/arm_gic_common.c > @@ -127,7 +127,11 @@ static void arm_gic_common_reset(DeviceState *dev) > int i; > memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); > for (i = 0 ; i < s->num_cpu; i++) { > - s->priority_mask[i] = 0xf0; > + if (s->revision == REV_11MPCORE) { > + s->priority_mask[i] = 0xf0; > + } else { > + s->priority_mask[i] = 0; > + } > s->current_pending[i] = 1023; > s->running_irq[i] = 1023; > s->running_priority[i] = 0x100; > diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c > index f0a2e7b..4963678 100644 > --- a/hw/armv7m_nvic.c > +++ b/hw/armv7m_nvic.c > @@ -455,9 +455,11 @@ static void armv7m_nvic_reset(DeviceState *dev) > nc->parent_reset(dev); > /* Common GIC reset resets to disabled; the NVIC doesn't have > * per-CPU interfaces so mark our non-existent CPU interface > - * as enabled by default. > + * as enabled by default, and with a priority mask which allows > + * all interrupts through. > */ > s->gic.cpu_enabled[0] = 1; > + s->gic.priority_mask[0] = 0x100; > /* The NVIC as a whole is always enabled. */ > s->gic.enabled = 1; > systick_reset(s); > Reviewed-by: Igor Mitsyanko