From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47584) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TiYmr-0003sm-Lw for qemu-devel@nongnu.org; Tue, 11 Dec 2012 17:58:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TiYml-00017J-S4 for qemu-devel@nongnu.org; Tue, 11 Dec 2012 17:58:53 -0500 Received: from mail-we0-f173.google.com ([74.125.82.173]:43151) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TiYml-00017E-Lg for qemu-devel@nongnu.org; Tue, 11 Dec 2012 17:58:47 -0500 Received: by mail-we0-f173.google.com with SMTP id z2so4860wey.4 for ; Tue, 11 Dec 2012 14:58:46 -0800 (PST) Message-ID: <50C7BAA5.2020603@gmail.com> Date: Tue, 11 Dec 2012 23:58:45 +0100 From: Antoine Mathys MIME-Version: 1.0 References: <50C7B767.8020406@gmail.com> In-Reply-To: <50C7B767.8020406@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH v2 5/6] hw/ds1338.c: Implement support for the control register. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , paul@codesourcery.com The previous patch has the side effect of clearing the control register. That's already its proper power-on-reset value. Signed-off-by: Antoine Mathys --- hw/ds1338.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/ds1338.c b/hw/ds1338.c index 5a6234b..319c341 100644 --- a/hw/ds1338.c +++ b/hw/ds1338.c @@ -125,7 +125,8 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) s->addr_byte = false; return 0; } - if (s->ptr < 8) { + if (s->ptr < 7) { + /* Time register. */ struct tm now; qemu_get_timedate(&now, s->offset); switch(s->ptr) { @@ -162,11 +163,19 @@ static int ds1338_send(I2CSlave *i2c, uint8_t data) case 6: now.tm_year = from_bcd(data) + 100; break; - case 7: - /* Control register. Currently ignored. */ - break; } s->offset = qemu_timedate_diff(&now); + } else if (s->ptr == 7) { + /* Control register. */ + + /* Ensure bits 2, 3 and 6 will read back as zero. */ + data &= 0xB3; + + /* Attempting to write the OSF flag to logic 1 leaves the + value unchanged. */ + data = (data & ~CTRL_OSF) | (data & s->nvram[s->ptr] & CTRL_OSF); + + s->nvram[s->ptr] = data; } else { s->nvram[s->ptr] = data; } -- 1.7.10.4