[Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14

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* [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14
@ 2012-12-14 12:13 Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 01/40] pseries: Fix incorrect initialization of interrupt controller Alexander Graf
                   ` (40 more replies)
  0 siblings, 41 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

Hi Blue / Aurelien,

This is my current patch queue for ppc.  Please pull.

Alex


The following changes since commit 1c97e303d4ea80a2691334b0febe87a50660f99d:
  Anthony Liguori (1):
        Merge remote-tracking branch 'afaerber/qom-cpu' into staging

are available in the git repository at:

  git://repo.or.cz/qemu/agraf.git ppc-for-upstream

Alexander Graf (27):
      openpic: Remove unused code
      mpic: Unify numbering scheme
      openpic: update to proper memory api
      openpic: combine mpic and openpic src handlers
      openpic: Convert subregions to memory api
      openpic: combine mpic and openpic irq raise functions
      openpic: merge mpic and openpic timer handling
      openpic: combine openpic and mpic reset functions
      openpic: unify memory api subregions
      openpic: remove unused type variable
      openpic: convert simple reg operations to builtin bitops
      openpic: rename openpic_t to OpenPICState
      openpic: remove irq_out
      openpic: convert to qdev
      openpic: make brr1 model specific
      openpic: add Shared MSI support
      PPC: e500: Add MSI support
      PPC: e500: Declare pci bridge as bridge
      MSI-X: Fix endianness
      openpic: fix minor coding style issues
      openpic: Accelerate pending irq search
      PPC: E500: PCI: Make first slot qdev settable
      PPC: E500: PCI: Make IRQ calculation more generic
      PPC: E500: Generate dt pci irq map dynamically
      PPC: E500: Move PCI slot information into params
      PPC: E500plat: Make a lot of PCI slots available
      PPC: e500: pci: Export slot2irq calculation

Ben Herrenschmidt (2):
      pseries: Use #define for XICS base irq number
      pseries: Allow RTAS tokens without a qemu handler

Bharat Bhushan (2):
      e500: Adding CCSR memory region
      Adding BAR0 for e500 PCI controller

David Gibson (8):
      pseries: Fix incorrect initialization of interrupt controller
      pseries: Add tracepoints to the XICS interrupt controller
      pseries: Split xics irq configuration from state information
      pseries: Implement PAPR NVRAM
      pseries: Update SLOF for NVRAM support
      pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs
      target-ppc: Don't use hwaddr to represent hardware state
      pseries: Increase default NVRAM size

Michael Ellerman (1):
      pseries: Return the token when we register an RTAS call

 hw/msix.c            |    6 +-
 hw/openpic.c         | 1397 ++++++++++++++++++--------------------------------
 hw/openpic.h         |    7 +-
 hw/ppc/Makefile.objs |    2 +-
 hw/ppc/e500-ccsr.h   |   17 +
 hw/ppc/e500.c        |  205 ++++++--
 hw/ppc/e500.h        |    2 +
 hw/ppc/e500plat.c    |    3 +
 hw/ppc/mpc8544ds.c   |    2 +
 hw/ppc_newworld.c    |   25 +-
 hw/ppce500_pci.c     |   58 ++-
 hw/ppce500_pci.h     |    9 +
 hw/spapr.c           |   35 ++-
 hw/spapr.h           |    4 +-
 hw/spapr_iommu.c     |    6 +
 hw/spapr_nvram.c     |  196 +++++++
 hw/spapr_rtas.c      |    6 +-
 hw/xics.c            |   47 ++-
 hw/xics.h            |    1 +
 pc-bios/README       |    2 +-
 pc-bios/slof.bin     |  Bin 878640 -> 880832 bytes
 qemu-config.c        |    4 +
 roms/SLOF            |    2 +-
 target-ppc/cpu.h     |    2 +-
 trace-events         |   13 +
 25 files changed, 1043 insertions(+), 1008 deletions(-)
 create mode 100644 hw/ppc/e500-ccsr.h
 create mode 100644 hw/ppce500_pci.h
 create mode 100644 hw/spapr_nvram.c

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 01/40] pseries: Fix incorrect initialization of interrupt controller
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 02/40] pseries: Use #define for XICS base irq number Alexander Graf
                   ` (39 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: David Gibson <david@gibson.dropbear.id.au>

Currently in the reset code for the XICS interrupt controller, we
initialize the pending_priority field to 0 (most favored, by XICS
convention).  This is incorrect, since there is no pending interrupt, it
should be set to least favored - 0xff.  At the moment our XICS
implementation doesn't get hurt by this edge case, but it does confuse the
upcoming kernel XICS implementation.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/xics.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/hw/xics.c b/hw/xics.c
index 1da3106..edf5833 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -495,7 +495,7 @@ static void xics_reset(void *opaque)
 
     for (i = 0; i < icp->nr_servers; i++) {
         icp->ss[i].xirr = 0;
-        icp->ss[i].pending_priority = 0;
+        icp->ss[i].pending_priority = 0xff;
         icp->ss[i].mfrr = 0xff;
         /* Make all outputs are deasserted */
         qemu_set_irq(icp->ss[i].output, 0);
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 02/40] pseries: Use #define for XICS base irq number
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 01/40] pseries: Fix incorrect initialization of interrupt controller Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 03/40] pseries: Return the token when we register an RTAS call Alexander Graf
                   ` (38 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List
  Cc: Michael Ellerman, qemu-devel qemu-devel, David Gibson

From: Ben Herrenschmidt <benh@kernel.crashing.org>

Currently the lowest "real" irq number for the XICS irq controller (as
opposed to numbers reserved for IPIs and other special purposes) is
hard coded as 16 in two places - in xics_system_init() and in spapr.c.

As well as being generally bad practice, we're going to need to change this
number soon to fit in with the in-kernel XICS implementation.  This patch
adds a #define for this number to avoid future breakage.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/spapr.c |    2 +-
 hw/xics.c  |    2 +-
 hw/xics.h  |    1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/spapr.c b/hw/spapr.c
index ad3f0ea..eafee03 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -801,7 +801,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
 
     /* Set up Interrupt Controller */
     spapr->icp = xics_system_init(XICS_IRQS);
-    spapr->next_irq = 16;
+    spapr->next_irq = XICS_IRQ_BASE;
 
     /* Set up EPOW events infrastructure */
     spapr_events_init(spapr);
diff --git a/hw/xics.c b/hw/xics.c
index edf5833..b8887cd 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -549,7 +549,7 @@ struct icp_state *xics_system_init(int nr_irqs)
 
     ics = g_malloc0(sizeof(*ics));
     ics->nr_irqs = nr_irqs;
-    ics->offset = 16;
+    ics->offset = XICS_IRQ_BASE;
     ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
 
     icp->ics = ics;
diff --git a/hw/xics.h b/hw/xics.h
index 6817268..c3bf008 100644
--- a/hw/xics.h
+++ b/hw/xics.h
@@ -28,6 +28,7 @@
 #define __XICS_H__
 
 #define XICS_IPI        0x2
+#define XICS_IRQ_BASE   0x10
 
 struct icp_state;
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 03/40] pseries: Return the token when we register an RTAS call
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 01/40] pseries: Fix incorrect initialization of interrupt controller Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 02/40] pseries: Use #define for XICS base irq number Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 04/40] pseries: Allow RTAS tokens without a qemu handler Alexander Graf
                   ` (37 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List
  Cc: Michael Ellerman, qemu-devel qemu-devel, David Gibson

From: Michael Ellerman <michael@ellerman.id.au>

The kernel will soon be able to service some RTAS calls. However the
choice of tokens will still be up to userspace. To support this have
spapr_rtas_register() return the token that is allocated for an
RTAS call, that allows the calling code to tell the kernel what the
token value is.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/spapr.h      |    2 +-
 hw/spapr_rtas.c |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/spapr.h b/hw/spapr.h
index efe7f57..971a50a 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -320,7 +320,7 @@ static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 typedef void (*spapr_rtas_fn)(sPAPREnvironment *spapr, uint32_t token,
                               uint32_t nargs, target_ulong args,
                               uint32_t nret, target_ulong rets);
-void spapr_rtas_register(const char *name, spapr_rtas_fn fn);
+int spapr_rtas_register(const char *name, spapr_rtas_fn fn);
 target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
                              uint32_t token, uint32_t nargs, target_ulong args,
                              uint32_t nret, target_ulong rets);
diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
index 6d5c48a..45294e8 100644
--- a/hw/spapr_rtas.c
+++ b/hw/spapr_rtas.c
@@ -242,7 +242,7 @@ target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
     return H_PARAMETER;
 }
 
-void spapr_rtas_register(const char *name, spapr_rtas_fn fn)
+int spapr_rtas_register(const char *name, spapr_rtas_fn fn)
 {
     int i;
 
@@ -258,7 +258,7 @@ void spapr_rtas_register(const char *name, spapr_rtas_fn fn)
     rtas_next->name = name;
     rtas_next->fn = fn;
 
-    rtas_next++;
+    return (rtas_next++ - rtas_table) + TOKEN_BASE;
 }
 
 int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 04/40] pseries: Allow RTAS tokens without a qemu handler
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (2 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 03/40] pseries: Return the token when we register an RTAS call Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 05/40] pseries: Add tracepoints to the XICS interrupt controller Alexander Graf
                   ` (36 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: Ben Herrenschmidt <benh@kernel.crashing.org>

Kernel-based RTAS calls will not have a qemu handler, but will
still be registered in qemu in order to be assigned a token
number and appear in the device-tree.

Let's test for the name being NULL rather than the handler
when deciding to skip an entry while building the device-tree

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/spapr_rtas.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
index 45294e8..e618c2d 100644
--- a/hw/spapr_rtas.c
+++ b/hw/spapr_rtas.c
@@ -301,7 +301,7 @@ int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
     for (i = 0; i < TOKEN_MAX; i++) {
         struct rtas_call *call = &rtas_table[i];
 
-        if (!call->fn) {
+        if (!call->name) {
             continue;
         }
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 05/40] pseries: Add tracepoints to the XICS interrupt controller
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (3 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 04/40] pseries: Allow RTAS tokens without a qemu handler Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 06/40] pseries: Split xics irq configuration from state information Alexander Graf
                   ` (35 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: David Gibson <david@gibson.dropbear.id.au>

This patch adds tracing / debugging calls to the XICS interrupt controller
implementation used on the pseries machine.

Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/xics.c    |   23 ++++++++++++++++++++---
 trace-events |   13 +++++++++++++
 2 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/hw/xics.c b/hw/xics.c
index b8887cd..33f99c7 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -26,6 +26,7 @@
  */
 
 #include "hw.h"
+#include "trace.h"
 #include "hw/spapr.h"
 #include "hw/xics.h"
 
@@ -66,6 +67,8 @@ static void icp_check_ipi(struct icp_state *icp, int server)
         return;
     }
 
+    trace_xics_icp_check_ipi(server, ss->mfrr);
+
     if (XISR(ss)) {
         ics_reject(icp->ics, XISR(ss));
     }
@@ -120,11 +123,13 @@ static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr)
 
 static uint32_t icp_accept(struct icp_server_state *ss)
 {
-    uint32_t xirr;
+    uint32_t xirr = ss->xirr;
 
     qemu_irq_lower(ss->output);
-    xirr = ss->xirr;
     ss->xirr = ss->pending_priority << 24;
+
+    trace_xics_icp_accept(xirr, ss->xirr);
+
     return xirr;
 }
 
@@ -134,6 +139,7 @@ static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
 
     /* Send EOI -> ICS */
     ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
+    trace_xics_icp_eoi(server, xirr, ss->xirr);
     ics_eoi(icp->ics, xirr & XISR_MASK);
     if (!XISR(ss)) {
         icp_resend(icp, server);
@@ -144,6 +150,8 @@ static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
 {
     struct icp_server_state *ss = icp->ss + server;
 
+    trace_xics_icp_irq(server, nr, priority);
+
     if ((priority >= CPPR(ss))
         || (XISR(ss) && (ss->pending_priority <= priority))) {
         ics_reject(icp->ics, nr);
@@ -153,6 +161,7 @@ static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
         }
         ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
         ss->pending_priority = priority;
+        trace_xics_icp_raise(ss->xirr, ss->pending_priority);
         qemu_irq_raise(ss->output);
     }
 }
@@ -217,10 +226,12 @@ static void set_irq_msi(struct ics_state *ics, int srcno, int val)
 {
     struct ics_irq_state *irq = ics->irqs + srcno;
 
+    trace_xics_set_irq_msi(srcno, srcno + ics->offset);
+
     if (val) {
         if (irq->priority == 0xff) {
             irq->status |= XICS_STATUS_MASKED_PENDING;
-            /* masked pending */ ;
+            trace_xics_masked_pending();
         } else  {
             icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
         }
@@ -231,6 +242,7 @@ static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
 {
     struct ics_irq_state *irq = ics->irqs + srcno;
 
+    trace_xics_set_irq_lsi(srcno, srcno + ics->offset);
     if (val) {
         irq->status |= XICS_STATUS_ASSERTED;
     } else {
@@ -279,6 +291,8 @@ static void ics_write_xive(struct ics_state *ics, int nr, int server,
     irq->priority = priority;
     irq->saved_priority = saved_priority;
 
+    trace_xics_ics_write_xive(nr, srcno, server, priority);
+
     if (irq->lsi) {
         write_xive_lsi(ics, srcno);
     } else {
@@ -290,6 +304,7 @@ static void ics_reject(struct ics_state *ics, int nr)
 {
     struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
 
+    trace_xics_ics_reject(nr, nr - ics->offset);
     irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
     irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
 }
@@ -315,6 +330,8 @@ static void ics_eoi(struct ics_state *ics, int nr)
     int srcno = nr - ics->offset;
     struct ics_irq_state *irq = ics->irqs + srcno;
 
+    trace_xics_ics_eoi(nr);
+
     if (irq->lsi) {
         irq->status &= ~XICS_STATUS_SENT;
     }
diff --git a/trace-events b/trace-events
index 6c6cbf1..6cb450a 100644
--- a/trace-events
+++ b/trace-events
@@ -1022,3 +1022,16 @@ spapr_pci_rtas_ibm_change_msi(unsigned func, unsigned req) "func %u, requested %
 spapr_pci_rtas_ibm_query_interrupt_source_number(unsigned ioa, unsigned intr) "queries for #%u, IRQ%u"
 spapr_pci_msi_write(uint64_t addr, uint64_t data, uint32_t dt_irq) "@%"PRIx64"<=%"PRIx64" IRQ %u"
 spapr_pci_lsi_set(const char *busname, int pin, uint32_t irq) "%s PIN%d IRQ %u"
+
+# hw/xics.c
+xics_icp_check_ipi(int server, uint8_t mfrr) "CPU %d can take IPI mfrr=%#x"
+xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr) "icp_accept: XIRR %#"PRIx32"->%#"PRIx32
+xics_icp_eoi(int server, uint32_t xirr, uint32_t new_xirr) "icp_eoi: server %d given XIRR %#"PRIx32" new XIRR %#"PRIx32
+xics_icp_irq(int server, int nr, uint8_t priority) "cpu %d trying to deliver irq %#"PRIx32" priority %#x"
+xics_icp_raise(uint32_t xirr, uint8_t pending_priority) "raising IRQ new XIRR=%#x new pending priority=%#x"
+xics_set_irq_msi(int srcno, int nr) "set_irq_msi: srcno %d [irq %#x]"
+xics_masked_pending(void) "set_irq_msi: masked pending"
+xics_set_irq_lsi(int srcno, int nr) "set_irq_lsi: srcno %d [irq %#x]"
+xics_ics_write_xive(int nr, int srcno, int server, uint8_t priority) "ics_write_xive: irq %#x [src %d] server %#x prio %#x"
+xics_ics_reject(int nr, int srcno) "reject irq %#x [src %d]"
+xics_ics_eoi(int nr) "ics_eoi: irq %#x"
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 06/40] pseries: Split xics irq configuration from state information
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (4 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 05/40] pseries: Add tracepoints to the XICS interrupt controller Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 07/40] pseries: Implement PAPR NVRAM Alexander Graf
                   ` (34 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: David Gibson <david@gibson.dropbear.id.au>

Currently the XICS irq controller code has a per-irq state structure which
amongst other things includes whether the interrupt is level or message
triggered - this is configured by the platform code, and is not directly
visible to the guest.  This leads to a slightly awkward construct at reset
time where we need to reset everything in the state structure _except_ the
lsi/msi flag, which needs to retain the information given at platform init
time.

More importantly this flag will make matching the qemu state to the KVM
state for the upcoming in-kernel XICS implementation more awkward.  This
patch, therefore, removes this flag from the per-irq state structure,
instead adding a parallel array giving the lsi/msi configuration per irq.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/xics.c |   20 ++++++++------------
 1 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/hw/xics.c b/hw/xics.c
index 33f99c7..55899ce 100644
--- a/hw/xics.c
+++ b/hw/xics.c
@@ -179,13 +179,13 @@ struct ics_irq_state {
 #define XICS_STATUS_REJECTED           0x4
 #define XICS_STATUS_MASKED_PENDING     0x8
     uint8_t status;
-    bool lsi;
 };
 
 struct ics_state {
     int nr_irqs;
     int offset;
     qemu_irq *qirqs;
+    bool *islsi;
     struct ics_irq_state *irqs;
     struct icp_state *icp;
 };
@@ -254,9 +254,8 @@ static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
 static void ics_set_irq(void *opaque, int srcno, int val)
 {
     struct ics_state *ics = (struct ics_state *)opaque;
-    struct ics_irq_state *irq = ics->irqs + srcno;
 
-    if (irq->lsi) {
+    if (ics->islsi[srcno]) {
         set_irq_lsi(ics, srcno, val);
     } else {
         set_irq_msi(ics, srcno, val);
@@ -293,7 +292,7 @@ static void ics_write_xive(struct ics_state *ics, int nr, int server,
 
     trace_xics_ics_write_xive(nr, srcno, server, priority);
 
-    if (irq->lsi) {
+    if (ics->islsi[srcno]) {
         write_xive_lsi(ics, srcno);
     } else {
         write_xive_msi(ics, srcno);
@@ -314,10 +313,8 @@ static void ics_resend(struct ics_state *ics)
     int i;
 
     for (i = 0; i < ics->nr_irqs; i++) {
-        struct ics_irq_state *irq = ics->irqs + i;
-
         /* FIXME: filter by server#? */
-        if (irq->lsi) {
+        if (ics->islsi[i]) {
             resend_lsi(ics, i);
         } else {
             resend_msi(ics, i);
@@ -332,7 +329,7 @@ static void ics_eoi(struct ics_state *ics, int nr)
 
     trace_xics_ics_eoi(nr);
 
-    if (irq->lsi) {
+    if (ics->islsi[srcno]) {
         irq->status &= ~XICS_STATUS_SENT;
     }
 }
@@ -354,7 +351,7 @@ void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi)
 {
     assert(ics_valid_irq(icp->ics, irq));
 
-    icp->ics->irqs[irq - icp->ics->offset].lsi = lsi;
+    icp->ics->islsi[irq - icp->ics->offset] = lsi;
 }
 
 static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
@@ -518,10 +515,8 @@ static void xics_reset(void *opaque)
         qemu_set_irq(icp->ss[i].output, 0);
     }
 
+    memset(ics->irqs, 0, sizeof(struct ics_irq_state) * ics->nr_irqs);
     for (i = 0; i < ics->nr_irqs; i++) {
-        /* Reset everything *except* the type */
-        ics->irqs[i].server = 0;
-        ics->irqs[i].status = 0;
         ics->irqs[i].priority = 0xff;
         ics->irqs[i].saved_priority = 0xff;
     }
@@ -568,6 +563,7 @@ struct icp_state *xics_system_init(int nr_irqs)
     ics->nr_irqs = nr_irqs;
     ics->offset = XICS_IRQ_BASE;
     ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
+    ics->islsi = g_malloc0(nr_irqs * sizeof(bool));
 
     icp->ics = ics;
     ics->icp = icp;
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 07/40] pseries: Implement PAPR NVRAM
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (5 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 06/40] pseries: Split xics irq configuration from state information Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 08/40] pseries: Update SLOF for NVRAM support Alexander Graf
                   ` (33 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: David Gibson <david@gibson.dropbear.id.au>

The PAPR specification requires a certain amount of NVRAM, accessed via
RTAS, which we don't currently implement in qemu.  This patch addresses
this deficiency, implementing the NVRAM as a VIO device, with some glue to
instantiate it automatically based on a machine option.

The machine option specifies a drive id, which is used to back the NVRAM,
making it persistent.  If nothing is specified, the driver instead simply
allocates space for the NVRAM, which will not be persistent

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/Makefile.objs |    2 +-
 hw/spapr.c           |   33 +++++++++
 hw/spapr.h           |    2 +
 hw/spapr_nvram.c     |  196 ++++++++++++++++++++++++++++++++++++++++++++++++++
 qemu-config.c        |    4 +
 5 files changed, 236 insertions(+), 1 deletions(-)
 create mode 100644 hw/spapr_nvram.c

diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 8fe2123..4492127 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -11,7 +11,7 @@ obj-y += ppc_newworld.o
 obj-$(CONFIG_PSERIES) += spapr.o spapr_hcall.o spapr_rtas.o spapr_vio.o
 obj-$(CONFIG_PSERIES) += xics.o spapr_vty.o spapr_llan.o spapr_vscsi.o
 obj-$(CONFIG_PSERIES) += spapr_pci.o pci-hotplug.o spapr_iommu.o
-obj-$(CONFIG_PSERIES) += spapr_events.o
+obj-$(CONFIG_PSERIES) += spapr_events.o spapr_nvram.o
 # PowerPC 4xx boards
 obj-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
 obj-y += ppc440_bamboo.o
diff --git a/hw/spapr.c b/hw/spapr.c
index eafee03..d23aa9d 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -657,6 +657,36 @@ static void spapr_cpu_reset(void *opaque)
         (spapr->htab_shift - 18);
 }
 
+static void spapr_create_nvram(sPAPREnvironment *spapr)
+{
+    QemuOpts *machine_opts;
+    DeviceState *dev;
+
+    dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
+
+    machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
+    if (machine_opts) {
+        const char *drivename;
+
+        drivename = qemu_opt_get(machine_opts, "nvram");
+        if (drivename) {
+            BlockDriverState *bs;
+
+            bs = bdrv_find(drivename);
+            if (!bs) {
+                fprintf(stderr, "No such block device \"%s\" for nvram\n",
+                        drivename);
+                exit(1);
+            }
+            qdev_prop_set_drive_nofail(dev, "drive", bs);
+        }
+    }
+
+    qdev_init_nofail(dev);
+
+    spapr->nvram = (struct sPAPRNVRAM *)dev;
+}
+
 /* Returns whether we want to use VGA or not */
 static int spapr_vga_init(PCIBus *pci_bus)
 {
@@ -818,6 +848,9 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args)
         }
     }
 
+    /* We always have at least the nvram device on VIO */
+    spapr_create_nvram(spapr);
+
     /* Set up PCI */
     spapr_pci_rtas_init();
 
diff --git a/hw/spapr.h b/hw/spapr.h
index 971a50a..600722f 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -6,11 +6,13 @@
 
 struct VIOsPAPRBus;
 struct sPAPRPHBState;
+struct sPAPRNVRAM;
 struct icp_state;
 
 typedef struct sPAPREnvironment {
     struct VIOsPAPRBus *vio_bus;
     QLIST_HEAD(, sPAPRPHBState) phbs;
+    struct sPAPRNVRAM *nvram;
     struct icp_state *icp;
 
     hwaddr ram_limit;
diff --git a/hw/spapr_nvram.c b/hw/spapr_nvram.c
new file mode 100644
index 0000000..641de48
--- /dev/null
+++ b/hw/spapr_nvram.c
@@ -0,0 +1,196 @@
+/*
+ * QEMU sPAPR NVRAM emulation
+ *
+ * Copyright (C) 2012 David Gibson, IBM Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include <sys/mman.h>
+#include <libfdt.h>
+
+#include "device_tree.h"
+#include "hw/sysbus.h"
+#include "hw/spapr.h"
+#include "hw/spapr_vio.h"
+
+typedef struct sPAPRNVRAM {
+    VIOsPAPRDevice sdev;
+    uint32_t size;
+    uint8_t *buf;
+    BlockDriverState *drive;
+} sPAPRNVRAM;
+
+#define MIN_NVRAM_SIZE 8192
+#define DEFAULT_NVRAM_SIZE 16384
+#define MAX_NVRAM_SIZE (UINT16_MAX * 16)
+
+static void rtas_nvram_fetch(sPAPREnvironment *spapr,
+                             uint32_t token, uint32_t nargs,
+                             target_ulong args,
+                             uint32_t nret, target_ulong rets)
+{
+    sPAPRNVRAM *nvram = spapr->nvram;
+    hwaddr offset, buffer, len;
+    int alen;
+    void *membuf;
+
+    if ((nargs != 3) || (nret != 2)) {
+        rtas_st(rets, 0, -3);
+        return;
+    }
+
+    if (!nvram) {
+        rtas_st(rets, 0, -1);
+        rtas_st(rets, 1, 0);
+        return;
+    }
+
+    offset = rtas_ld(args, 0);
+    buffer = rtas_ld(args, 1);
+    len = rtas_ld(args, 2);
+
+    if (((offset + len) < offset)
+        || ((offset + len) > nvram->size)) {
+        rtas_st(rets, 0, -3);
+        rtas_st(rets, 1, 0);
+        return;
+    }
+
+    membuf = cpu_physical_memory_map(buffer, &len, 1);
+    if (nvram->drive) {
+        alen = bdrv_pread(nvram->drive, offset, membuf, len);
+    } else {
+        assert(nvram->buf);
+
+        memcpy(membuf, nvram->buf + offset, len);
+        alen = len;
+    }
+    cpu_physical_memory_unmap(membuf, len, 1, len);
+
+    rtas_st(rets, 0, (alen < len) ? -1 : 0);
+    rtas_st(rets, 1, (alen < 0) ? 0 : alen);
+}
+
+static void rtas_nvram_store(sPAPREnvironment *spapr,
+                             uint32_t token, uint32_t nargs,
+                             target_ulong args,
+                             uint32_t nret, target_ulong rets)
+{
+    sPAPRNVRAM *nvram = spapr->nvram;
+    hwaddr offset, buffer, len;
+    int alen;
+    void *membuf;
+
+    if ((nargs != 3) || (nret != 2)) {
+        rtas_st(rets, 0, -3);
+        return;
+    }
+
+    if (!nvram) {
+        rtas_st(rets, 0, -1);
+        return;
+    }
+
+    offset = rtas_ld(args, 0);
+    buffer = rtas_ld(args, 1);
+    len = rtas_ld(args, 2);
+
+    if (((offset + len) < offset)
+        || ((offset + len) > nvram->size)) {
+        rtas_st(rets, 0, -3);
+        return;
+    }
+
+    membuf = cpu_physical_memory_map(buffer, &len, 0);
+    if (nvram->drive) {
+        alen = bdrv_pwrite(nvram->drive, offset, membuf, len);
+    } else {
+        assert(nvram->buf);
+
+        memcpy(nvram->buf + offset, membuf, len);
+        alen = len;
+    }
+    cpu_physical_memory_unmap(membuf, len, 0, len);
+
+    rtas_st(rets, 0, (alen < len) ? -1 : 0);
+    rtas_st(rets, 1, (alen < 0) ? 0 : alen);
+}
+
+static int spapr_nvram_init(VIOsPAPRDevice *dev)
+{
+    sPAPRNVRAM *nvram = (sPAPRNVRAM *)dev;
+
+    if (nvram->drive) {
+        nvram->size = bdrv_getlength(nvram->drive);
+    } else {
+        nvram->size = DEFAULT_NVRAM_SIZE;
+        nvram->buf = g_malloc0(nvram->size);
+    }
+
+    if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) {
+        fprintf(stderr, "spapr-nvram must be between %d and %d bytes in size\n",
+                MIN_NVRAM_SIZE, MAX_NVRAM_SIZE);
+        return -1;
+    }
+
+    spapr_rtas_register("nvram-fetch", rtas_nvram_fetch);
+    spapr_rtas_register("nvram-store", rtas_nvram_store);
+
+    return 0;
+}
+
+static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off)
+{
+    sPAPRNVRAM *nvram = (sPAPRNVRAM *)dev;
+
+    return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
+}
+
+static Property spapr_nvram_properties[] = {
+    DEFINE_SPAPR_PROPERTIES(sPAPRNVRAM, sdev),
+    DEFINE_PROP_DRIVE("drive", sPAPRNVRAM, drive),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void spapr_nvram_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    VIOsPAPRDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass);
+
+    k->init = spapr_nvram_init;
+    k->devnode = spapr_nvram_devnode;
+    k->dt_name = "nvram";
+    k->dt_type = "nvram";
+    k->dt_compatible = "qemu,spapr-nvram";
+    dc->props = spapr_nvram_properties;
+}
+
+static const TypeInfo spapr_nvram_type_info = {
+    .name          = "spapr-nvram",
+    .parent        = TYPE_VIO_SPAPR_DEVICE,
+    .instance_size = sizeof(sPAPRNVRAM),
+    .class_init    = spapr_nvram_class_init,
+};
+
+static void spapr_nvram_register_types(void)
+{
+    type_register_static(&spapr_nvram_type_info);
+}
+
+type_init(spapr_nvram_register_types)
diff --git a/qemu-config.c b/qemu-config.c
index aa78fb9..de10051 100644
--- a/qemu-config.c
+++ b/qemu-config.c
@@ -579,6 +579,10 @@ static QemuOptsList qemu_machine_opts = {
             .name = "usb",
             .type = QEMU_OPT_BOOL,
             .help = "Set on/off to enable/disable usb",
+        }, {
+            .name = "nvram",
+            .type = QEMU_OPT_STRING,
+            .help = "Drive backing persistent NVRAM",
         },
         { /* End of list */ }
     },
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 08/40] pseries: Update SLOF for NVRAM support
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (6 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 07/40] pseries: Implement PAPR NVRAM Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 09/40] e500: Adding CCSR memory region Alexander Graf
                   ` (32 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: David Gibson <david@gibson.dropbear.id.au>

Now that we have implemented PAPR compatible NVRAM interfaces in qemu, this
updates the SLOF firmware to actually initialize and use the NVRAM as a
PAPR guest firmware is expected to do.

This SLOF update also includes an ugly but useful workaround for a bug in
the SLES11 installer which caused it to fail under KVM.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 pc-bios/README   |    2 +-
 pc-bios/slof.bin |  Bin 878640 -> 880832 bytes
 roms/SLOF        |    2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/pc-bios/README b/pc-bios/README
index 3037130..eff3de7 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -17,7 +17,7 @@
 - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware
   implementation for certain IBM POWER hardware.  The sources are at
   https://github.com/dgibson/SLOF, and the image currently in qemu is
-  built from git tag qemu-slof-20120731.
+  built from git tag qemu-slof-20121018.

 - sgabios (the Serial Graphics Adapter option ROM) provides a means for
   legacy x86 software to communicate with an attached serial console as
diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin
index 84ba6b83f3c7fe523cb0b0e73ae8522872d1feef..3410f4fff40ff4a93d8963bf63fd6c1439f8b19c 100644
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diff --git a/roms/SLOF b/roms/SLOF
index f21f7a3..0ad10f2 160000
--- a/roms/SLOF
+++ b/roms/SLOF
@@ -1 +1 @@
-Subproject commit f21f7a3f46b557eb5923f899ce8b4401b3cc6d91
+Subproject commit 0ad10f26c94a86a0c9c3970e53f9a9f6a744055d
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 09/40] e500: Adding CCSR memory region
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (7 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 08/40] pseries: Update SLOF for NVRAM support Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 13:47   ` Andreas Färber
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller Alexander Graf
                   ` (31 subsequent siblings)
  40 siblings, 1 reply; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List
  Cc: Bharat Bhushan, qemu-devel qemu-devel, Bharat Bhushan

From: Bharat Bhushan <r65777@freescale.com>

All devices are also placed under CCSR memory region.
The CCSR memory region is exported to pci device. The MSI interrupt
generation is the main reason to export the CCSR region to PCI device.
This put the requirement to move mpic under CCSR region, but logically
all devices should be under CCSR. So this patch places all emulated
devices under ccsr region.

Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/e500.c |   63 ++++++++++++++++++++++++++++++++++++--------------------
 1 files changed, 40 insertions(+), 23 deletions(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 6749fff..8538933 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -46,13 +46,15 @@
 /* TODO: parameterize */
 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
-#define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000ULL)
-#define MPC8544_SERIAL0_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4500ULL)
-#define MPC8544_SERIAL1_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4600ULL)
-#define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + 0x8000ULL)
+#define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
+#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
+#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
+#define MPC8544_PCI_REGS_OFFSET    0x8000ULL
+#define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + \
+                                    MPC8544_PCI_REGS_OFFSET)
 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
 #define MPC8544_PCI_IO             0xE1000000ULL
-#define MPC8544_UTIL_BASE          (MPC8544_CCSRBAR_BASE + 0xe0000ULL)
+#define MPC8544_UTIL_OFFSET        0xe0000ULL
 #define MPC8544_SPIN_BASE          0xEF000000ULL
 
 struct boot_info
@@ -267,13 +269,12 @@ static int ppce500_load_device_tree(CPUPPCState *env,
     /* XXX should contain a reasonable value */
     qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
 
-    snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc,
-             MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE);
+    snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
     qemu_devtree_add_subnode(fdt, mpic);
     qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
     qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");
-    qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE -
-                               MPC8544_CCSRBAR_BASE, 0x40000);
+    qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
+                               0x40000);
     qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
     qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
     mpic_ph = qemu_devtree_alloc_phandle(fdt);
@@ -286,17 +287,16 @@ static int ppce500_load_device_tree(CPUPPCState *env,
      * device it finds in the dt as serial output device. And we generate
      * devices in reverse order to the dt.
      */
-    dt_serial_create(fdt, MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE,
+    dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
                      soc, mpic, "serial1", 1, false);
-    dt_serial_create(fdt, MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE,
+    dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
                      soc, mpic, "serial0", 0, true);
 
     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
-             MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE);
+             MPC8544_UTIL_OFFSET);
     qemu_devtree_add_subnode(fdt, gutil);
     qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
-    qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE -
-                               MPC8544_CCSRBAR_BASE, 0x1000);
+    qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 
     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
@@ -422,6 +422,8 @@ void ppce500_init(PPCE500Params *params)
     qemu_irq **irqs, *mpic;
     DeviceState *dev;
     CPUPPCState *firstenv = NULL;
+    MemoryRegion *ccsr;
+    SysBusDevice *s;
 
     /* Setup CPUs */
     if (params->cpu_model == NULL) {
@@ -450,7 +452,8 @@ void ppce500_init(PPCE500Params *params)
         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
         env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
-        env->mpic_cpu_base = MPC8544_MPIC_REGS_BASE + 0x20000;
+        env->mpic_cpu_base = MPC8544_CCSRBAR_BASE +
+                              MPC8544_MPIC_REGS_OFFSET + 0x20000;
 
         ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
 
@@ -477,8 +480,12 @@ void ppce500_init(PPCE500Params *params)
     vmstate_register_ram_global(ram);
     memory_region_add_subregion(address_space_mem, 0, ram);
 
+    ccsr = g_malloc0(sizeof(MemoryRegion));
+    memory_region_init(ccsr, "e500-ccsr", MPC8544_CCSRBAR_SIZE);
+    memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, ccsr);
+
     /* MPIC */
-    mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
+    mpic = mpic_init(ccsr, MPC8544_MPIC_REGS_OFFSET,
                      smp_cpus, irqs, NULL);
 
     if (!mpic) {
@@ -487,25 +494,35 @@ void ppce500_init(PPCE500Params *params)
 
     /* Serial */
     if (serial_hds[0]) {
-        serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
+        serial_mm_init(ccsr, MPC8544_SERIAL0_REGS_OFFSET,
                        0, mpic[12+26], 399193,
                        serial_hds[0], DEVICE_BIG_ENDIAN);
     }
 
     if (serial_hds[1]) {
-        serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
+        serial_mm_init(ccsr, MPC8544_SERIAL1_REGS_OFFSET,
                        0, mpic[12+26], 399193,
                        serial_hds[1], DEVICE_BIG_ENDIAN);
     }
 
     /* General Utility device */
-    sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
+    dev = qdev_create(NULL, "mpc8544-guts");
+    qdev_init_nofail(dev);
+    s = SYS_BUS_DEVICE(dev);
+    memory_region_add_subregion(ccsr, MPC8544_UTIL_OFFSET,
+                                sysbus_mmio_get_region(s, 0));
 
     /* PCI */
-    dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
-                                mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
-                                mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
-                                NULL);
+    dev = qdev_create(NULL, "e500-pcihost");
+    qdev_init_nofail(dev);
+    s = SYS_BUS_DEVICE(dev);
+    sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
+    sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
+    sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
+    sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
+    memory_region_add_subregion(ccsr, MPC8544_PCI_REGS_OFFSET,
+                                sysbus_mmio_get_region(s, 0));
+
     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
     if (!pci_bus)
         printf("couldn't create PCI controller!\n");
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* Re: [Qemu-devel] [PATCH 09/40] e500: Adding CCSR memory region
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 09/40] e500: Adding CCSR memory region Alexander Graf
@ 2012-12-14 13:47   ` Andreas Färber
  0 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-12-14 13:47 UTC (permalink / raw)
  To: Alexander Graf
  Cc: Bharat Bhushan, qemu-ppc@nongnu.org List, qemu-devel qemu-devel,
	Bharat Bhushan

Am 14.12.2012 13:13, schrieb Alexander Graf:
> From: Bharat Bhushan <r65777@freescale.com>
> 
> All devices are also placed under CCSR memory region.
> The CCSR memory region is exported to pci device. The MSI interrupt
> generation is the main reason to export the CCSR region to PCI device.
> This put the requirement to move mpic under CCSR region, but logically
> all devices should be under CCSR. So this patch places all emulated
> devices under ccsr region.
> 
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>

Reviewed-by: Andreas Färber <afaerber@suse.de>

> Signed-off-by: Alexander Graf <agraf@suse.de>

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (8 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 09/40] e500: Adding CCSR memory region Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 13:49   ` Andreas Färber
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 11/40] pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs Alexander Graf
                   ` (30 subsequent siblings)
  40 siblings, 1 reply; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List
  Cc: Bharat Bhushan, qemu-devel qemu-devel, Bharat Bhushan

From: Bharat Bhushan <r65777@freescale.com>

PCI Root complex have TYPE-1 configuration header while PCI endpoint
have type-0 configuration header. The type-1 configuration header have
a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
address space to CCSR address space. This can used for 2 purposes: 1)
for MSI interrupt generation 2) Allow CCSR registers access when configured
as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest.

What I observed is that when guest read the size of BAR0 of host controller
configuration header (TYPE1 header) then it always reads it as 0. When
looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller
device registering BAR0. I do not find any other controller also doing so
may they do not use BAR0.

There are two issues when BAR0 is not there (which I can think of):
1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and
when reading the size of BAR0, it should give size as per real h/w.

2) Do we need this BAR0 inbound address translation?
        When BAR0 is of non-zero size then it will be configured for PCI
address space to local address(CCSR) space translation on inbound access.
The primary use case is for MSI interrupt generation. The device is
configured with an address offsets in PCI address space, which will be
translated to MSI interrupt generation MPIC registers. Currently I do
not understand the MSI interrupt generation mechanism in QEMU and also
IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines.
But this BAR0 will be used when using MSI on e500.

I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c,
but i do not see these being used for address translation.
So far that works because pci address space and local address space are 1:1
mapped. BAR0 inbound translation + ATMU translation will complete the address
translation of inbound traffic.

Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
[agraf: fix double variable assignment w/o read]
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/e500-ccsr.h |   17 ++++++++++++++++
 hw/ppc/e500.c      |   55 +++++++++++++++++++++++++++++++++++++++++++--------
 hw/ppce500_pci.c   |   29 ++++++++++++++++++++++++++-
 3 files changed, 91 insertions(+), 10 deletions(-)
 create mode 100644 hw/ppc/e500-ccsr.h

diff --git a/hw/ppc/e500-ccsr.h b/hw/ppc/e500-ccsr.h
new file mode 100644
index 0000000..f20f51b
--- /dev/null
+++ b/hw/ppc/e500-ccsr.h
@@ -0,0 +1,17 @@
+#ifndef E500_CCSR_H
+#define E500_CCSR_H
+
+#include "../sysbus.h"
+
+typedef struct PPCE500CCSRState {
+    /*< private >*/
+    SysBusDevice parent;
+    /*< public >*/
+
+    MemoryRegion ccsr_space;
+} PPCE500CCSRState;
+
+#define TYPE_CCSR "e500-ccsr"
+#define CCSR(obj) OBJECT_CHECK(PPCE500CCSRState, (obj), TYPE_CCSR)
+
+#endif /* E500_CCSR_H */
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 8538933..47e2d41 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -17,6 +17,7 @@
 #include "config.h"
 #include "qemu-common.h"
 #include "e500.h"
+#include "e500-ccsr.h"
 #include "net.h"
 #include "hw/hw.h"
 #include "hw/serial.h"
@@ -422,8 +423,9 @@ void ppce500_init(PPCE500Params *params)
     qemu_irq **irqs, *mpic;
     DeviceState *dev;
     CPUPPCState *firstenv = NULL;
-    MemoryRegion *ccsr;
+    MemoryRegion *ccsr_addr_space;
     SysBusDevice *s;
+    PPCE500CCSRState *ccsr;
 
     /* Setup CPUs */
     if (params->cpu_model == NULL) {
@@ -480,12 +482,17 @@ void ppce500_init(PPCE500Params *params)
     vmstate_register_ram_global(ram);
     memory_region_add_subregion(address_space_mem, 0, ram);
 
-    ccsr = g_malloc0(sizeof(MemoryRegion));
-    memory_region_init(ccsr, "e500-ccsr", MPC8544_CCSRBAR_SIZE);
-    memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, ccsr);
+    dev = qdev_create(NULL, "e500-ccsr");
+    object_property_add_child(qdev_get_machine(), "e500-ccsr",
+                              OBJECT(dev), NULL);
+    qdev_init_nofail(dev);
+    ccsr = CCSR(dev);
+    ccsr_addr_space = &ccsr->ccsr_space;
+    memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
+                                ccsr_addr_space);
 
     /* MPIC */
-    mpic = mpic_init(ccsr, MPC8544_MPIC_REGS_OFFSET,
+    mpic = mpic_init(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
                      smp_cpus, irqs, NULL);
 
     if (!mpic) {
@@ -494,13 +501,13 @@ void ppce500_init(PPCE500Params *params)
 
     /* Serial */
     if (serial_hds[0]) {
-        serial_mm_init(ccsr, MPC8544_SERIAL0_REGS_OFFSET,
+        serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
                        0, mpic[12+26], 399193,
                        serial_hds[0], DEVICE_BIG_ENDIAN);
     }
 
     if (serial_hds[1]) {
-        serial_mm_init(ccsr, MPC8544_SERIAL1_REGS_OFFSET,
+        serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
                        0, mpic[12+26], 399193,
                        serial_hds[1], DEVICE_BIG_ENDIAN);
     }
@@ -509,7 +516,7 @@ void ppce500_init(PPCE500Params *params)
     dev = qdev_create(NULL, "mpc8544-guts");
     qdev_init_nofail(dev);
     s = SYS_BUS_DEVICE(dev);
-    memory_region_add_subregion(ccsr, MPC8544_UTIL_OFFSET,
+    memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
                                 sysbus_mmio_get_region(s, 0));
 
     /* PCI */
@@ -520,7 +527,7 @@ void ppce500_init(PPCE500Params *params)
     sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
     sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
     sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
-    memory_region_add_subregion(ccsr, MPC8544_PCI_REGS_OFFSET,
+    memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
                                 sysbus_mmio_get_region(s, 0));
 
     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
@@ -595,3 +602,33 @@ void ppce500_init(PPCE500Params *params)
         kvmppc_init();
     }
 }
+
+static int e500_ccsr_initfn(SysBusDevice *dev)
+{
+    PPCE500CCSRState *ccsr;
+
+    ccsr = CCSR(dev);
+    memory_region_init(&ccsr->ccsr_space, "e500-ccsr",
+                       MPC8544_CCSRBAR_SIZE);
+    return 0;
+}
+
+static void e500_ccsr_class_init(ObjectClass *klass, void *data)
+{
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+    k->init = e500_ccsr_initfn;
+}
+
+static const TypeInfo e500_ccsr_info = {
+    .name          = TYPE_CCSR,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(PPCE500CCSRState),
+    .class_init    = e500_ccsr_class_init,
+};
+
+static void e500_register_types(void)
+{
+    type_register_static(&e500_ccsr_info);
+}
+
+type_init(e500_register_types)
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 2ff7438..54c72b4 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -15,6 +15,7 @@
  */
 
 #include "hw.h"
+#include "hw/ppc/e500-ccsr.h"
 #include "pci.h"
 #include "pci_host.h"
 #include "bswap.h"
@@ -92,6 +93,19 @@ struct PPCE500PCIState {
     MemoryRegion pio;
 };
 
+#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
+#define PPC_E500_PCI_BRIDGE(obj) \
+    OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
+
+struct PPCE500PCIBridgeState {
+    /*< private >*/
+    PCIDevice parent;
+    /*< public >*/
+
+    MemoryRegion bar0;
+};
+
+typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
 typedef struct PPCE500PCIState PPCE500PCIState;
 
 static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
@@ -310,6 +324,18 @@ static const VMStateDescription vmstate_ppce500_pci = {
 
 #include "exec-memory.h"
 
+static int e500_pcihost_bridge_initfn(PCIDevice *d)
+{
+    PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
+    PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
+                                  "/e500-ccsr"));
+
+    memory_region_init_alias(&b->bar0, "e500-pci-bar0", &ccsr->ccsr_space,
+                             0, int128_get64(ccsr->ccsr_space.size));
+    pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
+    return 0;
+}
+
 static int e500_pcihost_initfn(SysBusDevice *dev)
 {
     PCIHostState *h;
@@ -355,6 +381,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
     DeviceClass *dc = DEVICE_CLASS(klass);
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 
+    k->init = e500_pcihost_bridge_initfn;
     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
     k->device_id = PCI_DEVICE_ID_MPC8533E;
     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
@@ -364,7 +391,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
 static const TypeInfo e500_host_bridge_info = {
     .name          = "e500-host-bridge",
     .parent        = TYPE_PCI_DEVICE,
-    .instance_size = sizeof(PCIDevice),
+    .instance_size = sizeof(PPCE500PCIBridgeState),
     .class_init    = e500_host_bridge_class_init,
 };
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* Re: [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller Alexander Graf
@ 2012-12-14 13:49   ` Andreas Färber
  0 siblings, 0 replies; 47+ messages in thread
From: Andreas Färber @ 2012-12-14 13:49 UTC (permalink / raw)
  To: Alexander Graf
  Cc: Bharat Bhushan, qemu-ppc@nongnu.org List, qemu-devel qemu-devel,
	Bharat Bhushan

Am 14.12.2012 13:13, schrieb Alexander Graf:
> From: Bharat Bhushan <r65777@freescale.com>
> 
> PCI Root complex have TYPE-1 configuration header while PCI endpoint
> have type-0 configuration header. The type-1 configuration header have
> a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
> address space to CCSR address space. This can used for 2 purposes: 1)
> for MSI interrupt generation 2) Allow CCSR registers access when configured
> as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest.
> 
> What I observed is that when guest read the size of BAR0 of host controller
> configuration header (TYPE1 header) then it always reads it as 0. When
> looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller
> device registering BAR0. I do not find any other controller also doing so
> may they do not use BAR0.
> 
> There are two issues when BAR0 is not there (which I can think of):
> 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and
> when reading the size of BAR0, it should give size as per real h/w.
> 
> 2) Do we need this BAR0 inbound address translation?
>         When BAR0 is of non-zero size then it will be configured for PCI
> address space to local address(CCSR) space translation on inbound access.
> The primary use case is for MSI interrupt generation. The device is
> configured with an address offsets in PCI address space, which will be
> translated to MSI interrupt generation MPIC registers. Currently I do
> not understand the MSI interrupt generation mechanism in QEMU and also
> IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines.
> But this BAR0 will be used when using MSI on e500.
> 
> I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c,
> but i do not see these being used for address translation.
> So far that works because pci address space and local address space are 1:1
> mapped. BAR0 inbound translation + ATMU translation will complete the address
> translation of inbound traffic.
> 
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> [agraf: fix double variable assignment w/o read]
> Signed-off-by: Alexander Graf <agraf@suse.de>

Reviewed-by: Andreas Färber <afaerber@suse.de>

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 11/40] pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (9 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 12/40] openpic: Remove unused code Alexander Graf
                   ` (29 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: David Gibson <david@gibson.dropbear.id.au>

The PAPR specification requires that every bus or device mediated by the
IOMMU have a unique Logical IO Bus Number (LIOBN).  This patch adds a check
to enforce this, which will help catch errors in configuration earlier.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/spapr_iommu.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/hw/spapr_iommu.c b/hw/spapr_iommu.c
index 02d78cc..3011b25 100644
--- a/hw/spapr_iommu.c
+++ b/hw/spapr_iommu.c
@@ -120,6 +120,12 @@ DMAContext *spapr_tce_new_dma_context(uint32_t liobn, size_t window_size)
 {
     sPAPRTCETable *tcet;
 
+    if (spapr_tce_find_by_liobn(liobn)) {
+        fprintf(stderr, "Attempted to create TCE table with duplicate"
+                " LIOBN 0x%x\n", liobn);
+        return NULL;
+    }
+
     if (!window_size) {
         return NULL;
     }
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 12/40] openpic: Remove unused code
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (10 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 11/40] pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 13/40] mpic: Unify numbering scheme Alexander Graf
                   ` (28 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The openpic code had a few WIP bits left that nobody reanimated within
the last few years. Remove that code.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hervé Poussineau <hpoussin@reactos.org>
---
 hw/openpic.c |  163 ----------------------------------------------------------
 1 files changed, 0 insertions(+), 163 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 8b3784a..b30c853 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -46,27 +46,8 @@
 #define DPRINTF(fmt, ...) do { } while (0)
 #endif
 
-#define USE_MPCxxx /* Intel model is broken, for now */
-
-#if defined (USE_INTEL_GW80314)
-/* Intel GW80314 I/O Companion chip */
-
-#define MAX_CPU     4
-#define MAX_IRQ    32
-#define MAX_DBL     4
-#define MAX_MBX     4
-#define MAX_TMR     4
-#define VECTOR_BITS 8
-#define MAX_IPI     4
-
-#define VID (0x00000000)
-
-#elif defined(USE_MPCxxx)
-
 #define MAX_CPU    15
 #define MAX_IRQ   128
-#define MAX_DBL     0
-#define MAX_MBX     0
 #define MAX_TMR     4
 #define VECTOR_BITS 8
 #define MAX_IPI     4
@@ -149,12 +130,6 @@ enum mpic_ide_bits {
     IDR_P0     = 0,
 };
 
-#else
-#error "Please select which OpenPic implementation is to be emulated"
-#endif
-
-#define OPENPIC_PAGE_SIZE 4096
-
 #define BF_WIDTH(_bits_) \
 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
 
@@ -250,19 +225,6 @@ typedef struct openpic_t {
         uint32_t ticc;  /* Global timer current count register */
         uint32_t tibc;  /* Global timer base count register */
     } timers[MAX_TMR];
-#if MAX_DBL > 0
-    /* Doorbell registers */
-    uint32_t dar;        /* Doorbell activate register */
-    struct {
-        uint32_t dmr;    /* Doorbell messaging register */
-    } doorbells[MAX_DBL];
-#endif
-#if MAX_MBX > 0
-    /* Mailbox registers */
-    struct {
-        uint32_t mbr;    /* Mailbox register */
-    } mailboxes[MAX_MAILBOXES];
-#endif
     /* IRQ out is used when in bypass mode (not implemented) */
     qemu_irq irq_out;
     int max_irq;
@@ -470,19 +432,6 @@ static void openpic_reset (void *opaque)
         opp->timers[i].ticc = 0x00000000;
         opp->timers[i].tibc = 0x80000000;
     }
-    /* Initialise doorbells */
-#if MAX_DBL > 0
-    opp->dar = 0x00000000;
-    for (i = 0; i < MAX_DBL; i++) {
-        opp->doorbells[i].dmr  = 0x00000000;
-    }
-#endif
-    /* Initialise mailboxes */
-#if MAX_MBX > 0
-    for (i = 0; i < MAX_MBX; i++) { /* ? */
-        opp->mailboxes[i].mbr   = 0x00000000;
-    }
-#endif
     /* Go out of RESET state */
     opp->glbc = 0x00000000;
 }
@@ -518,84 +467,6 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
             opp->src[n_IRQ].ipvp);
 }
 
-#if 0 // Code provision for Intel model
-#if MAX_DBL > 0
-static uint32_t read_doorbell_register (openpic_t *opp,
-                                        int n_dbl, uint32_t offset)
-{
-    uint32_t retval;
-
-    switch (offset) {
-    case DBL_IPVP_OFFSET:
-        retval = read_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl);
-        break;
-    case DBL_IDE_OFFSET:
-        retval = read_IRQreg_ide(opp, IRQ_DBL0 + n_dbl);
-        break;
-    case DBL_DMR_OFFSET:
-        retval = opp->doorbells[n_dbl].dmr;
-        break;
-    }
-
-    return retval;
-}
-
-static void write_doorbell_register (penpic_t *opp, int n_dbl,
-                                     uint32_t offset, uint32_t value)
-{
-    switch (offset) {
-    case DBL_IVPR_OFFSET:
-        write_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl, value);
-        break;
-    case DBL_IDE_OFFSET:
-        write_IRQreg_ide(opp, IRQ_DBL0 + n_dbl, value);
-        break;
-    case DBL_DMR_OFFSET:
-        opp->doorbells[n_dbl].dmr = value;
-        break;
-    }
-}
-#endif
-
-#if MAX_MBX > 0
-static uint32_t read_mailbox_register (openpic_t *opp,
-                                       int n_mbx, uint32_t offset)
-{
-    uint32_t retval;
-
-    switch (offset) {
-    case MBX_MBR_OFFSET:
-        retval = opp->mailboxes[n_mbx].mbr;
-        break;
-    case MBX_IVPR_OFFSET:
-        retval = read_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx);
-        break;
-    case MBX_DMR_OFFSET:
-        retval = read_IRQreg_ide(opp, IRQ_MBX0 + n_mbx);
-        break;
-    }
-
-    return retval;
-}
-
-static void write_mailbox_register (openpic_t *opp, int n_mbx,
-                                    uint32_t address, uint32_t value)
-{
-    switch (offset) {
-    case MBX_MBR_OFFSET:
-        opp->mailboxes[n_mbx].mbr = value;
-        break;
-    case MBX_IVPR_OFFSET:
-        write_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx, value);
-        break;
-    case MBX_DMR_OFFSET:
-        write_IRQreg_ide(opp, IRQ_MBX0 + n_mbx, value);
-        break;
-    }
-}
-#endif
-#endif /* 0 : Code provision for Intel model */
-
 static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
 {
     openpic_t *opp = opaque;
@@ -841,7 +712,6 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
     dst = &opp->dst[idx];
     addr &= 0xFF0;
     switch (addr) {
-#if MAX_IPI > 0
     case 0x40: /* IPIDR */
     case 0x50:
     case 0x60:
@@ -853,7 +723,6 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
         openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
         openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
         break;
-#endif
     case 0x80: /* PCTP */
         dst->pctp = val & 0x0000000F;
         break;
@@ -1109,20 +978,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
         qemu_put_be32s(f, &opp->timers[i].tibc);
     }
 
-#if MAX_DBL > 0
-    qemu_put_be32s(f, &opp->dar);
-
-    for (i = 0; i < MAX_DBL; i++) {
-        qemu_put_be32s(f, &opp->doorbells[i].dmr);
-    }
-#endif
-
-#if MAX_MBX > 0
-    for (i = 0; i < MAX_MAILBOXES; i++) {
-        qemu_put_be32s(f, &opp->mailboxes[i].mbr);
-    }
-#endif
-
     pci_device_save(&opp->pci_dev, f);
 }
 
@@ -1176,20 +1031,6 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
         qemu_get_be32s(f, &opp->timers[i].tibc);
     }
 
-#if MAX_DBL > 0
-    qemu_get_be32s(f, &opp->dar);
-
-    for (i = 0; i < MAX_DBL; i++) {
-        qemu_get_be32s(f, &opp->doorbells[i].dmr);
-    }
-#endif
-
-#if MAX_MBX > 0
-    for (i = 0; i < MAX_MAILBOXES; i++) {
-        qemu_get_be32s(f, &opp->mailboxes[i].mbr);
-    }
-#endif
-
     return pci_device_load(&opp->pci_dev, f);
 }
 
@@ -1222,11 +1063,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
     for (; i < OPENPIC_IRQ_TIM0; i++) {
         opp->src[i].type = IRQ_SPECIAL;
     }
-#if MAX_IPI > 0
     m = OPENPIC_IRQ_IPI0;
-#else
-    m = OPENPIC_IRQ_DBL0;
-#endif
     for (; i < m; i++) {
         opp->src[i].type = IRQ_TIMER;
     }
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 13/40] mpic: Unify numbering scheme
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (11 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 12/40] openpic: Remove unused code Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 14/40] openpic: update to proper memory api Alexander Graf
                   ` (27 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

MPIC interrupt numbers in Linux (device tree) and in QEMU are different,
because QEMU takes the sparseness of the IRQ number space into account.

Remove that cleverness and instead assume a flat number space. This makes
the code easier to understand, because we are actually aligned with Linux
on the view of our worlds.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c  |  290 +++++++++------------------------------------------------
 hw/ppc/e500.c |    4 +-
 2 files changed, 45 insertions(+), 249 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index b30c853..122ce76 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -46,11 +46,12 @@
 #define DPRINTF(fmt, ...) do { } while (0)
 #endif
 
-#define MAX_CPU    15
-#define MAX_IRQ   128
+#define MAX_CPU     15
+#define MAX_SRC     256
 #define MAX_TMR     4
 #define VECTOR_BITS 8
 #define MAX_IPI     4
+#define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
 #define VID         0x03 /* MPIC version ID */
 #define VENI        0x00000000 /* Vendor ID */
 
@@ -82,32 +83,25 @@ enum {
 #define MPIC_MAX_CPU      1
 #define MPIC_MAX_EXT     12
 #define MPIC_MAX_INT     64
-#define MPIC_MAX_MSG      4
-#define MPIC_MAX_MSI      8
-#define MPIC_MAX_TMR      MAX_TMR
-#define MPIC_MAX_IPI      MAX_IPI
-#define MPIC_MAX_IRQ     (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
+#define MPIC_MAX_IRQ     MAX_IRQ
 
 /* Interrupt definitions */
-#define MPIC_EXT_IRQ      0
-#define MPIC_INT_IRQ      (MPIC_EXT_IRQ + MPIC_MAX_EXT)
-#define MPIC_TMR_IRQ      (MPIC_INT_IRQ + MPIC_MAX_INT)
-#define MPIC_MSG_IRQ      (MPIC_TMR_IRQ + MPIC_MAX_TMR)
-#define MPIC_MSI_IRQ      (MPIC_MSG_IRQ + MPIC_MAX_MSG)
-#define MPIC_IPI_IRQ      (MPIC_MSI_IRQ + MPIC_MAX_MSI)
+/* IRQs, accessible through the IRQ region */
+#define MPIC_EXT_IRQ      0x00
+#define MPIC_INT_IRQ      0x10
+#define MPIC_MSG_IRQ      0xb0
+#define MPIC_MSI_IRQ      0xe0
+/* These are available through separate regions, but
+   for simplicity's sake mapped into the same number space */
+#define MPIC_TMR_IRQ      0x100
+#define MPIC_IPI_IRQ      0x104
 
 #define MPIC_GLB_REG_START        0x0
 #define MPIC_GLB_REG_SIZE         0x10F0
 #define MPIC_TMR_REG_START        0x10F0
 #define MPIC_TMR_REG_SIZE         0x220
-#define MPIC_EXT_REG_START        0x10000
-#define MPIC_EXT_REG_SIZE         0x180
-#define MPIC_INT_REG_START        0x10200
-#define MPIC_INT_REG_SIZE         0x800
-#define MPIC_MSG_REG_START        0x11600
-#define MPIC_MSG_REG_SIZE         0x100
-#define MPIC_MSI_REG_START        0x11C00
-#define MPIC_MSI_REG_SIZE         0x100
+#define MPIC_IRQ_REG_START        0x10000
+#define MPIC_IRQ_REG_SIZE         (MAX_SRC * 0x20)
 #define MPIC_CPU_REG_START        0x20000
 #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
 
@@ -1205,193 +1199,44 @@ static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
     return retval;
 }
 
-static void mpic_src_ext_write (void *opaque, hwaddr addr,
-                                uint32_t val)
+static void mpic_src_irq_write(void *opaque, hwaddr addr,
+                               uint64_t val, unsigned len)
 {
     openpic_t *mpp = opaque;
-    int idx = MPIC_EXT_IRQ;
+    int idx = addr / 0x20;
 
-    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
-    if (addr & 0xF)
-        return;
-
-    if (addr < MPIC_EXT_REG_SIZE) {
-        idx += (addr & 0xFFF0) >> 5;
-        if (addr & 0x10) {
-            /* EXDE / IFEDE / IEEDE */
-            write_IRQreg_ide(mpp, idx, val);
-        } else {
-            /* EXVP / IFEVP / IEEVP */
-            write_IRQreg_ipvp(mpp, idx, val);
-        }
-    }
-}
-
-static uint32_t mpic_src_ext_read (void *opaque, hwaddr addr)
-{
-    openpic_t *mpp = opaque;
-    uint32_t retval;
-    int idx = MPIC_EXT_IRQ;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-    retval = 0xFFFFFFFF;
-    if (addr & 0xF)
-        return retval;
-
-    if (addr < MPIC_EXT_REG_SIZE) {
-        idx += (addr & 0xFFF0) >> 5;
-        if (addr & 0x10) {
-            /* EXDE / IFEDE / IEEDE */
-            retval = read_IRQreg_ide(mpp, idx);
-        } else {
-            /* EXVP / IFEVP / IEEVP */
-            retval = read_IRQreg_ipvp(mpp, idx);
-        }
-        DPRINTF("%s: => %08x\n", __func__, retval);
-    }
-
-    return retval;
-}
-
-static void mpic_src_int_write (void *opaque, hwaddr addr,
-                                uint32_t val)
-{
-    openpic_t *mpp = opaque;
-    int idx = MPIC_INT_IRQ;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
-    if (addr & 0xF)
-        return;
-
-    if (addr < MPIC_INT_REG_SIZE) {
-        idx += (addr & 0xFFF0) >> 5;
-        if (addr & 0x10) {
-            /* EXDE / IFEDE / IEEDE */
-            write_IRQreg_ide(mpp, idx, val);
-        } else {
-            /* EXVP / IFEVP / IEEVP */
-            write_IRQreg_ipvp(mpp, idx, val);
-        }
-    }
-}
-
-static uint32_t mpic_src_int_read (void *opaque, hwaddr addr)
-{
-    openpic_t *mpp = opaque;
-    uint32_t retval;
-    int idx = MPIC_INT_IRQ;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-    retval = 0xFFFFFFFF;
-    if (addr & 0xF)
-        return retval;
-
-    if (addr < MPIC_INT_REG_SIZE) {
-        idx += (addr & 0xFFF0) >> 5;
-        if (addr & 0x10) {
-            /* EXDE / IFEDE / IEEDE */
-            retval = read_IRQreg_ide(mpp, idx);
-        } else {
-            /* EXVP / IFEVP / IEEVP */
-            retval = read_IRQreg_ipvp(mpp, idx);
-        }
-        DPRINTF("%s: => %08x\n", __func__, retval);
-    }
-
-    return retval;
-}
-
-static void mpic_src_msg_write (void *opaque, hwaddr addr,
-                                uint32_t val)
-{
-    openpic_t *mpp = opaque;
-    int idx = MPIC_MSG_IRQ;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
+    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08" PRIx64 "\n",
+            __func__, addr, val);
     if (addr & 0xF)
         return;
 
-    if (addr < MPIC_MSG_REG_SIZE) {
-        idx += (addr & 0xFFF0) >> 5;
-        if (addr & 0x10) {
-            /* EXDE / IFEDE / IEEDE */
-            write_IRQreg_ide(mpp, idx, val);
-        } else {
-            /* EXVP / IFEVP / IEEVP */
-            write_IRQreg_ipvp(mpp, idx, val);
-        }
-    }
-}
-
-static uint32_t mpic_src_msg_read (void *opaque, hwaddr addr)
-{
-    openpic_t *mpp = opaque;
-    uint32_t retval;
-    int idx = MPIC_MSG_IRQ;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-    retval = 0xFFFFFFFF;
-    if (addr & 0xF)
-        return retval;
-
-    if (addr < MPIC_MSG_REG_SIZE) {
-        idx += (addr & 0xFFF0) >> 5;
-        if (addr & 0x10) {
-            /* EXDE / IFEDE / IEEDE */
-            retval = read_IRQreg_ide(mpp, idx);
-        } else {
-            /* EXVP / IFEVP / IEEVP */
-            retval = read_IRQreg_ipvp(mpp, idx);
-        }
-        DPRINTF("%s: => %08x\n", __func__, retval);
+    if (addr & 0x10) {
+        /* EXDE / IFEDE / IEEDE */
+        write_IRQreg_ide(mpp, idx, val);
+    } else {
+        /* EXVP / IFEVP / IEEVP */
+        write_IRQreg_ipvp(mpp, idx, val);
     }
-
-    return retval;
 }
 
-static void mpic_src_msi_write (void *opaque, hwaddr addr,
-                                uint32_t val)
-{
-    openpic_t *mpp = opaque;
-    int idx = MPIC_MSI_IRQ;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
-    if (addr & 0xF)
-        return;
-
-    if (addr < MPIC_MSI_REG_SIZE) {
-        idx += (addr & 0xFFF0) >> 5;
-        if (addr & 0x10) {
-            /* EXDE / IFEDE / IEEDE */
-            write_IRQreg_ide(mpp, idx, val);
-        } else {
-            /* EXVP / IFEVP / IEEVP */
-            write_IRQreg_ipvp(mpp, idx, val);
-        }
-    }
-}
-static uint32_t mpic_src_msi_read (void *opaque, hwaddr addr)
+static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len)
 {
     openpic_t *mpp = opaque;
     uint32_t retval;
-    int idx = MPIC_MSI_IRQ;
+    int idx = addr / 0x20;
 
     DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-    retval = 0xFFFFFFFF;
     if (addr & 0xF)
-        return retval;
+        return -1;
 
-    if (addr < MPIC_MSI_REG_SIZE) {
-        idx += (addr & 0xFFF0) >> 5;
-        if (addr & 0x10) {
-            /* EXDE / IFEDE / IEEDE */
-            retval = read_IRQreg_ide(mpp, idx);
-        } else {
-            /* EXVP / IFEVP / IEEVP */
-            retval = read_IRQreg_ipvp(mpp, idx);
-        }
-        DPRINTF("%s: => %08x\n", __func__, retval);
+    if (addr & 0x10) {
+        /* EXDE / IFEDE / IEEDE */
+        retval = read_IRQreg_ide(mpp, idx);
+    } else {
+        /* EXVP / IFEVP / IEEVP */
+        retval = read_IRQreg_ipvp(mpp, idx);
     }
+    DPRINTF("%s: => %08x\n", __func__, retval);
 
     return retval;
 }
@@ -1438,60 +1283,14 @@ static const MemoryRegionOps mpic_cpu_ops = {
     .endianness = DEVICE_BIG_ENDIAN,
 };
 
-static const MemoryRegionOps mpic_ext_ops = {
-    .old_mmio = {
-        .write = { openpic_buggy_write,
-                   openpic_buggy_write,
-                   mpic_src_ext_write,
-        },
-        .read  = { openpic_buggy_read,
-                   openpic_buggy_read,
-                   mpic_src_ext_read,
-        },
-    },
-    .endianness = DEVICE_BIG_ENDIAN,
-};
-
-static const MemoryRegionOps mpic_int_ops = {
-    .old_mmio = {
-        .write = { openpic_buggy_write,
-                   openpic_buggy_write,
-                   mpic_src_int_write,
-        },
-        .read  = { openpic_buggy_read,
-                   openpic_buggy_read,
-                   mpic_src_int_read,
-        },
-    },
-    .endianness = DEVICE_BIG_ENDIAN,
-};
-
-static const MemoryRegionOps mpic_msg_ops = {
-    .old_mmio = {
-        .write = { openpic_buggy_write,
-                   openpic_buggy_write,
-                   mpic_src_msg_write,
-        },
-        .read  = { openpic_buggy_read,
-                   openpic_buggy_read,
-                   mpic_src_msg_read,
-        },
-    },
+static const MemoryRegionOps mpic_irq_ops = {
+    .write = mpic_src_irq_write,
+    .read  = mpic_src_irq_read,
     .endianness = DEVICE_BIG_ENDIAN,
-};
-
-static const MemoryRegionOps mpic_msi_ops = {
-    .old_mmio = {
-        .write = { openpic_buggy_write,
-                   openpic_buggy_write,
-                   mpic_src_msi_write,
-        },
-        .read  = { openpic_buggy_read,
-                   openpic_buggy_read,
-                   mpic_src_msi_read,
-        },
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
     },
-    .endianness = DEVICE_BIG_ENDIAN,
 };
 
 qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
@@ -1507,10 +1306,7 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
     } const list[] = {
         {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
         {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
-        {"ext", &mpic_ext_ops, MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
-        {"int", &mpic_int_ops, MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
-        {"msg", &mpic_msg_ops, MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
-        {"msi", &mpic_msi_ops, MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
+        {"irq", &mpic_irq_ops, MPIC_IRQ_REG_START, MPIC_IRQ_REG_SIZE},
         {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
     };
 
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 47e2d41..f3e97d8 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -502,13 +502,13 @@ void ppce500_init(PPCE500Params *params)
     /* Serial */
     if (serial_hds[0]) {
         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
-                       0, mpic[12+26], 399193,
+                       0, mpic[42], 399193,
                        serial_hds[0], DEVICE_BIG_ENDIAN);
     }
 
     if (serial_hds[1]) {
         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
-                       0, mpic[12+26], 399193,
+                       0, mpic[42], 399193,
                        serial_hds[1], DEVICE_BIG_ENDIAN);
     }
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 14/40] openpic: update to proper memory api
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (12 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 13/40] mpic: Unify numbering scheme Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 15/40] openpic: combine mpic and openpic src handlers Alexander Graf
                   ` (26 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The openpic code was still using the old mmio memory api. Convert it to
be a generic memory api user and clean up some code that becomes redundant
that way.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |  138 ++++++++++++++++++++--------------------------------------
 1 files changed, 48 insertions(+), 90 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 122ce76..1d714f4 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -461,7 +461,8 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
             opp->src[n_IRQ].ipvp);
 }
 
-static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
+static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
+                              unsigned len)
 {
     openpic_t *opp = opaque;
     IRQ_dst_t *dst;
@@ -527,7 +528,7 @@ static void openpic_gbl_write (void *opaque, hwaddr addr, uint32_t val)
     }
 }
 
-static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
+static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
 {
     openpic_t *opp = opaque;
     uint32_t retval;
@@ -584,7 +585,8 @@ static uint32_t openpic_gbl_read (void *opaque, hwaddr addr)
     return retval;
 }
 
-static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
+static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
+                                unsigned len)
 {
     openpic_t *opp = opaque;
     int idx;
@@ -615,7 +617,7 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
     }
 }
 
-static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
+static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
 {
     openpic_t *opp = opaque;
     uint32_t retval;
@@ -648,7 +650,8 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
     return retval;
 }
 
-static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
+static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
+                              unsigned len)
 {
     openpic_t *opp = opaque;
     int idx;
@@ -667,7 +670,7 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
     }
 }
 
-static uint32_t openpic_src_read (void *opaque, uint32_t addr)
+static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
 {
     openpic_t *opp = opaque;
     uint32_t retval;
@@ -749,7 +752,8 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
     }
 }
 
-static void openpic_cpu_write(void *opaque, hwaddr addr, uint32_t val)
+static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
+                              unsigned len)
 {
     openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
 }
@@ -833,96 +837,63 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
     return retval;
 }
 
-static uint32_t openpic_cpu_read(void *opaque, hwaddr addr)
+static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
 {
     return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
 }
 
-static void openpic_buggy_write (void *opaque,
-                                 hwaddr addr, uint32_t val)
-{
-    printf("Invalid OPENPIC write access !\n");
-}
-
-static uint32_t openpic_buggy_read (void *opaque, hwaddr addr)
-{
-    printf("Invalid OPENPIC read access !\n");
-
-    return -1;
-}
-
-static void openpic_writel (void *opaque,
-                            hwaddr addr, uint32_t val)
+static void openpic_write(void *opaque, hwaddr addr, uint64_t val,
+                          unsigned len)
 {
     openpic_t *opp = opaque;
 
-    addr &= 0x3FFFF;
     DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
     if (addr < 0x1100) {
         /* Global registers */
-        openpic_gbl_write(opp, addr, val);
+        openpic_gbl_write(opp, addr, val, len);
     } else if (addr < 0x10000) {
         /* Timers registers */
-        openpic_timer_write(opp, addr, val);
+        openpic_timer_write(opp, addr, val, len);
     } else if (addr < 0x20000) {
         /* Source registers */
-        openpic_src_write(opp, addr, val);
+        openpic_src_write(opp, addr, val, len);
     } else {
         /* CPU registers */
-        openpic_cpu_write(opp, addr, val);
+        openpic_cpu_write(opp, addr, val, len);
     }
 }
 
-static uint32_t openpic_readl (void *opaque,hwaddr addr)
+static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len)
 {
     openpic_t *opp = opaque;
     uint32_t retval;
 
-    addr &= 0x3FFFF;
     DPRINTF("%s: offset %08x\n", __func__, (int)addr);
     if (addr < 0x1100) {
         /* Global registers */
-        retval = openpic_gbl_read(opp, addr);
+        retval = openpic_gbl_read(opp, addr, len);
     } else if (addr < 0x10000) {
         /* Timers registers */
-        retval = openpic_timer_read(opp, addr);
+        retval = openpic_timer_read(opp, addr, len);
     } else if (addr < 0x20000) {
         /* Source registers */
-        retval = openpic_src_read(opp, addr);
+        retval = openpic_src_read(opp, addr, len);
     } else {
         /* CPU registers */
-        retval = openpic_cpu_read(opp, addr);
+        retval = openpic_cpu_read(opp, addr, len);
     }
 
     return retval;
 }
 
-static uint64_t openpic_read(void *opaque, hwaddr addr,
-                             unsigned size)
-{
-    openpic_t *opp = opaque;
-
-    switch (size) {
-    case 4: return openpic_readl(opp, addr);
-    default: return openpic_buggy_read(opp, addr);
-    }
-}
-
-static void openpic_write(void *opaque, hwaddr addr,
-                          uint64_t data, unsigned size)
-{
-    openpic_t *opp = opaque;
-
-    switch (size) {
-    case 4: return openpic_writel(opp, addr, data);
-    default: return openpic_buggy_write(opp, addr, data);
-    }
-}
-
 static const MemoryRegionOps openpic_ops = {
     .read = openpic_read,
     .write = openpic_write,
     .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
 };
 
 static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
@@ -1131,7 +1102,8 @@ static void mpic_reset (void *opaque)
     mpp->glbc = 0x00000000;
 }
 
-static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
+static void mpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
+                             unsigned len)
 {
     openpic_t *mpp = opaque;
     int idx, cpu;
@@ -1139,7 +1111,6 @@ static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
     DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
     if (addr & 0xF)
         return;
-    addr &= 0xFFFF;
     cpu = addr >> 12;
     idx = (addr >> 6) & 0x3;
     switch (addr & 0x30) {
@@ -1164,7 +1135,7 @@ static void mpic_timer_write (void *opaque, hwaddr addr, uint32_t val)
     }
 }
 
-static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
+static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len)
 {
     openpic_t *mpp = opaque;
     uint32_t retval;
@@ -1174,7 +1145,6 @@ static uint32_t mpic_timer_read (void *opaque, hwaddr addr)
     retval = 0xFFFFFFFF;
     if (addr & 0xF)
         return retval;
-    addr &= 0xFFFF;
     cpu = addr >> 12;
     idx = (addr >> 6) & 0x3;
     switch (addr & 0x30) {
@@ -1242,45 +1212,33 @@ static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len)
 }
 
 static const MemoryRegionOps mpic_glb_ops = {
-    .old_mmio = {
-        .write = { openpic_buggy_write,
-                   openpic_buggy_write,
-                   openpic_gbl_write,
-        },
-        .read  = { openpic_buggy_read,
-                   openpic_buggy_read,
-                   openpic_gbl_read,
-        },
-    },
+    .write = openpic_gbl_write,
+    .read  = openpic_gbl_read,
     .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
 };
 
 static const MemoryRegionOps mpic_tmr_ops = {
-    .old_mmio = {
-        .write = { openpic_buggy_write,
-                   openpic_buggy_write,
-                   mpic_timer_write,
-        },
-        .read  = { openpic_buggy_read,
-                   openpic_buggy_read,
-                   mpic_timer_read,
-        },
-    },
+    .write = mpic_timer_write,
+    .read  = mpic_timer_read,
     .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
 };
 
 static const MemoryRegionOps mpic_cpu_ops = {
-    .old_mmio = {
-        .write = { openpic_buggy_write,
-                   openpic_buggy_write,
-                   openpic_cpu_write,
-        },
-        .read  = { openpic_buggy_read,
-                   openpic_buggy_read,
-                   openpic_cpu_read,
-        },
-    },
+    .write = openpic_cpu_write,
+    .read  = openpic_cpu_read,
     .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
 };
 
 static const MemoryRegionOps mpic_irq_ops = {
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 15/40] openpic: combine mpic and openpic src handlers
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (13 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 14/40] openpic: update to proper memory api Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 16/40] openpic: Convert subregions to memory api Alexander Graf
                   ` (25 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The MPIC source irq handler suddenly became identical to the standard
OpenPIC source irq handler. Combine them into the same function.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   52 +++++-----------------------------------------------
 1 files changed, 5 insertions(+), 47 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 1d714f4..b671d9d 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -100,8 +100,8 @@ enum {
 #define MPIC_GLB_REG_SIZE         0x10F0
 #define MPIC_TMR_REG_START        0x10F0
 #define MPIC_TMR_REG_SIZE         0x220
-#define MPIC_IRQ_REG_START        0x10000
-#define MPIC_IRQ_REG_SIZE         (MAX_SRC * 0x20)
+#define MPIC_SRC_REG_START        0x10000
+#define MPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
 #define MPIC_CPU_REG_START        0x20000
 #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
 
@@ -1169,48 +1169,6 @@ static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len)
     return retval;
 }
 
-static void mpic_src_irq_write(void *opaque, hwaddr addr,
-                               uint64_t val, unsigned len)
-{
-    openpic_t *mpp = opaque;
-    int idx = addr / 0x20;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08" PRIx64 "\n",
-            __func__, addr, val);
-    if (addr & 0xF)
-        return;
-
-    if (addr & 0x10) {
-        /* EXDE / IFEDE / IEEDE */
-        write_IRQreg_ide(mpp, idx, val);
-    } else {
-        /* EXVP / IFEVP / IEEVP */
-        write_IRQreg_ipvp(mpp, idx, val);
-    }
-}
-
-static uint64_t mpic_src_irq_read(void *opaque, hwaddr addr, unsigned len)
-{
-    openpic_t *mpp = opaque;
-    uint32_t retval;
-    int idx = addr / 0x20;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-    if (addr & 0xF)
-        return -1;
-
-    if (addr & 0x10) {
-        /* EXDE / IFEDE / IEEDE */
-        retval = read_IRQreg_ide(mpp, idx);
-    } else {
-        /* EXVP / IFEVP / IEEVP */
-        retval = read_IRQreg_ipvp(mpp, idx);
-    }
-    DPRINTF("%s: => %08x\n", __func__, retval);
-
-    return retval;
-}
-
 static const MemoryRegionOps mpic_glb_ops = {
     .write = openpic_gbl_write,
     .read  = openpic_gbl_read,
@@ -1242,8 +1200,8 @@ static const MemoryRegionOps mpic_cpu_ops = {
 };
 
 static const MemoryRegionOps mpic_irq_ops = {
-    .write = mpic_src_irq_write,
-    .read  = mpic_src_irq_read,
+    .write = openpic_src_write,
+    .read  = openpic_src_read,
     .endianness = DEVICE_BIG_ENDIAN,
     .impl = {
         .min_access_size = 4,
@@ -1264,7 +1222,7 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
     } const list[] = {
         {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
         {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
-        {"irq", &mpic_irq_ops, MPIC_IRQ_REG_START, MPIC_IRQ_REG_SIZE},
+        {"src", &mpic_irq_ops, MPIC_SRC_REG_START, MPIC_SRC_REG_SIZE},
         {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
     };
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 16/40] openpic: Convert subregions to memory api
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (14 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 15/40] openpic: combine mpic and openpic src handlers Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 17/40] openpic: combine mpic and openpic irq raise functions Alexander Graf
                   ` (24 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The "openpic" controller is currently using one big region and does
subregion dispatching manually. Move this to the memory api.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |  106 +++++++++++++++++++++++++++++++++------------------------
 1 files changed, 61 insertions(+), 45 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index b671d9d..2a3b56a 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -79,6 +79,15 @@ enum {
 #define OPENPIC_IRQ_MBX0   (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
 #endif
 
+#define OPENPIC_GLB_REG_START        0x0
+#define OPENPIC_GLB_REG_SIZE         0x10F0
+#define OPENPIC_TMR_REG_START        0x10F0
+#define OPENPIC_TMR_REG_SIZE         0x220
+#define OPENPIC_SRC_REG_START        0x10000
+#define OPENPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
+#define OPENPIC_CPU_REG_START        0x20000
+#define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
+
 /* MPIC */
 #define MPIC_MAX_CPU      1
 #define MPIC_MAX_EXT     12
@@ -842,53 +851,39 @@ static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
     return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
 }
 
-static void openpic_write(void *opaque, hwaddr addr, uint64_t val,
-                          unsigned len)
-{
-    openpic_t *opp = opaque;
-
-    DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
-    if (addr < 0x1100) {
-        /* Global registers */
-        openpic_gbl_write(opp, addr, val, len);
-    } else if (addr < 0x10000) {
-        /* Timers registers */
-        openpic_timer_write(opp, addr, val, len);
-    } else if (addr < 0x20000) {
-        /* Source registers */
-        openpic_src_write(opp, addr, val, len);
-    } else {
-        /* CPU registers */
-        openpic_cpu_write(opp, addr, val, len);
-    }
-}
-
-static uint64_t openpic_read(void *opaque, hwaddr addr, unsigned len)
-{
-    openpic_t *opp = opaque;
-    uint32_t retval;
+static const MemoryRegionOps openpic_glb_ops = {
+    .write = openpic_gbl_write,
+    .read  = openpic_gbl_read,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
 
-    DPRINTF("%s: offset %08x\n", __func__, (int)addr);
-    if (addr < 0x1100) {
-        /* Global registers */
-        retval = openpic_gbl_read(opp, addr, len);
-    } else if (addr < 0x10000) {
-        /* Timers registers */
-        retval = openpic_timer_read(opp, addr, len);
-    } else if (addr < 0x20000) {
-        /* Source registers */
-        retval = openpic_src_read(opp, addr, len);
-    } else {
-        /* CPU registers */
-        retval = openpic_cpu_read(opp, addr, len);
-    }
+static const MemoryRegionOps openpic_tmr_ops = {
+    .write = openpic_timer_write,
+    .read  = openpic_timer_read,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
 
-    return retval;
-}
+static const MemoryRegionOps openpic_cpu_ops = {
+    .write = openpic_cpu_write,
+    .read  = openpic_cpu_read,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
 
-static const MemoryRegionOps openpic_ops = {
-    .read = openpic_read,
-    .write = openpic_write,
+static const MemoryRegionOps openpic_src_ops = {
+    .write = openpic_src_write,
+    .read  = openpic_src_read,
     .endianness = DEVICE_LITTLE_ENDIAN,
     .impl = {
         .min_access_size = 4,
@@ -1009,12 +1004,33 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
 {
     openpic_t *opp;
     int i, m;
+    struct {
+        const char             *name;
+        MemoryRegionOps const  *ops;
+        hwaddr      start_addr;
+        ram_addr_t              size;
+    } const list[] = {
+        {"glb", &openpic_glb_ops, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
+        {"tmr", &openpic_tmr_ops, OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
+        {"src", &openpic_src_ops, OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
+        {"cpu", &openpic_cpu_ops, OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
+    };
 
     /* XXX: for now, only one CPU is supported */
     if (nb_cpus != 1)
         return NULL;
     opp = g_malloc0(sizeof(openpic_t));
-    memory_region_init_io(&opp->mem, &openpic_ops, opp, "openpic", 0x40000);
+
+    memory_region_init(&opp->mem, "openpic", 0x40000);
+
+    for (i = 0; i < ARRAY_SIZE(list); i++) {
+
+        memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,
+                              list[i].name, list[i].size);
+
+        memory_region_add_subregion(&opp->mem, list[i].start_addr,
+                                    &opp->sub_io_mem[i]);
+    }
 
     //    isu_base &= 0xFFFC0000;
     opp->nb_cpus = nb_cpus;
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 17/40] openpic: combine mpic and openpic irq raise functions
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (15 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 16/40] openpic: Convert subregions to memory api Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 18/40] openpic: merge mpic and openpic timer handling Alexander Graf
                   ` (23 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The IRQ raise mechanisms of the OpenPIC and MPIC controllers is identical,
just that the MPIC one can also raise critical interrupts.

Combine those two and check for critical raise capability during runtime.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   34 ++++++++++++++++------------------
 hw/openpic.h |    3 +++
 2 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 2a3b56a..d709e36 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -207,6 +207,9 @@ typedef struct openpic_t {
     PCIDevice pci_dev;
     MemoryRegion mem;
 
+    /* Behavior control */
+    uint32_t flags;
+
     /* Sub-regions */
     MemoryRegion sub_io_mem[7];
 
@@ -234,9 +237,10 @@ typedef struct openpic_t {
     int irq_ipi0;
     int irq_tim0;
     void (*reset) (void *);
-    void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
 } openpic_t;
 
+static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
+
 static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
 {
     set_bit(q->queue, n_IRQ);
@@ -321,7 +325,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
         return;
     }
     DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ);
-    opp->irq_raise(opp, n_CPU, src);
+    openpic_irq_raise(opp, n_CPU, src);
 }
 
 /* update pic state because registers for n_IRQ have changed value */
@@ -753,7 +757,7 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
              IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) {
             DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
                     idx, n_IRQ);
-            opp->irq_raise(opp, idx, src);
+            openpic_irq_raise(opp, idx, src);
         }
         break;
     default:
@@ -996,7 +1000,13 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
 
 static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
 {
-    qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
+    int n_ci = IDR_CI0 - n_CPU;
+
+    if ((opp->flags & OPENPIC_FLAG_IDE_CRIT) && test_bit(&src->ide, n_ci)) {
+        qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
+    } else {
+        qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
+    }
 }
 
 qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
@@ -1059,7 +1069,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
                     openpic_save, openpic_load, opp);
     qemu_register_reset(openpic_reset, opp);
 
-    opp->irq_raise = openpic_irq_raise;
     opp->reset = openpic_reset;
 
     if (pmem)
@@ -1068,18 +1077,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
     return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
 }
 
-static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
-{
-    int n_ci = IDR_CI0 - n_CPU;
-
-    if(test_bit(&src->ide, n_ci)) {
-        qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
-    }
-    else {
-        qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
-    }
-}
-
 static void mpic_reset (void *opaque)
 {
     openpic_t *mpp = (openpic_t *)opaque;
@@ -1265,7 +1262,8 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
         mpp->dst[i].irqs = irqs[i];
     mpp->irq_out = irq_out;
 
-    mpp->irq_raise = mpic_irq_raise;
+    /* Enable critical interrupt support */
+    mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
     mpp->reset = mpic_reset;
 
     register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
diff --git a/hw/openpic.h b/hw/openpic.h
index f50a1e4..1232d10 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -11,6 +11,9 @@ enum {
     OPENPIC_OUTPUT_NB,
 };
 
+/* OpenPIC capability flags */
+#define OPENPIC_FLAG_IDE_CRIT    (1 << 0)
+
 qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
                         qemu_irq **irqs, qemu_irq irq_out);
 qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 18/40] openpic: merge mpic and openpic timer handling
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (16 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 17/40] openpic: combine mpic and openpic irq raise functions Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 19/40] openpic: combine openpic and mpic reset functions Alexander Graf
                   ` (22 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The openpic and mpic timer handling code is basically the same.
Merge them.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |  131 ++++++++++++++--------------------------------------------
 1 files changed, 31 insertions(+), 100 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index d709e36..80016a2 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -195,7 +195,6 @@ enum IPVP_bits {
 #define IPVP_VECTOR(_ipvpr_)   ((_ipvpr_) & IPVP_VECTOR_MASK)
 
 typedef struct IRQ_dst_t {
-    uint32_t tfrr;
     uint32_t pctp; /* CPU current task priority */
     uint32_t pcsr; /* CPU sensitivity register */
     IRQ_queue_t raised;
@@ -533,9 +532,6 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
     case 0x10E0: /* SPVE */
         opp->spve = val & 0x000000FF;
         break;
-    case 0x10F0: /* TIFR */
-        opp->tifr = val;
-        break;
     default:
         break;
     }
@@ -587,9 +583,6 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
     case 0x10E0: /* SPVE */
         retval = opp->spve;
         break;
-    case 0x10F0: /* TIFR */
-        retval = opp->tifr;
-        break;
     default:
         break;
     }
@@ -607,24 +600,28 @@ static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
     DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
     if (addr & 0xF)
         return;
-    addr -= 0x10;
-    addr &= 0xFFFF;
-    idx = (addr & 0xFFF0) >> 6;
+    idx = (addr >> 6) & 0x3;
     addr = addr & 0x30;
-    switch (addr) {
-    case 0x00: /* TICC */
+
+    if (addr == 0x0) {
+        /* TIFR (TFRR) */
+        opp->tifr = val;
+        return;
+    }
+    switch (addr & 0x30) {
+    case 0x00: /* TICC (GTCCR) */
         break;
-    case 0x10: /* TIBC */
+    case 0x10: /* TIBC (GTBCR) */
         if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
             (val & 0x80000000) == 0 &&
             (opp->timers[idx].tibc & 0x80000000) != 0)
             opp->timers[idx].ticc &= ~0x80000000;
         opp->timers[idx].tibc = val;
         break;
-    case 0x20: /* TIVP */
+    case 0x20: /* TIVP (GTIVPR) */
         write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val);
         break;
-    case 0x30: /* TIDE */
+    case 0x30: /* TIDE (GTIDR) */
         write_IRQreg_ide(opp, opp->irq_tim0 + idx, val);
         break;
     }
@@ -633,31 +630,35 @@ static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
 static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
 {
     openpic_t *opp = opaque;
-    uint32_t retval;
+    uint32_t retval = -1;
     int idx;
 
     DPRINTF("%s: addr %08x\n", __func__, addr);
-    retval = 0xFFFFFFFF;
-    if (addr & 0xF)
-        return retval;
-    addr -= 0x10;
-    addr &= 0xFFFF;
-    idx = (addr & 0xFFF0) >> 6;
-    addr = addr & 0x30;
-    switch (addr) {
-    case 0x00: /* TICC */
+    if (addr & 0xF) {
+        goto out;
+    }
+    idx = (addr >> 6) & 0x3;
+    if (addr == 0x0) {
+        /* TIFR (TFRR) */
+        retval = opp->tifr;
+        goto out;
+    }
+    switch (addr & 0x30) {
+    case 0x00: /* TICC (GTCCR) */
         retval = opp->timers[idx].ticc;
         break;
-    case 0x10: /* TIBC */
+    case 0x10: /* TIBC (GTBCR) */
         retval = opp->timers[idx].tibc;
         break;
-    case 0x20: /* TIPV */
+    case 0x20: /* TIPV (TIPV) */
         retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx);
         break;
-    case 0x30: /* TIDE */
+    case 0x30: /* TIDE (TIDR) */
         retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx);
         break;
     }
+
+out:
     DPRINTF("%s: => %08x\n", __func__, retval);
 
     return retval;
@@ -930,7 +931,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
     qemu_put_sbe32s(f, &opp->nb_cpus);
 
     for (i = 0; i < opp->nb_cpus; i++) {
-        qemu_put_be32s(f, &opp->dst[i].tfrr);
         qemu_put_be32s(f, &opp->dst[i].pctp);
         qemu_put_be32s(f, &opp->dst[i].pcsr);
         openpic_save_IRQ_queue(f, &opp->dst[i].raised);
@@ -983,7 +983,6 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
     qemu_get_sbe32s(f, &opp->nb_cpus);
 
     for (i = 0; i < opp->nb_cpus; i++) {
-        qemu_get_be32s(f, &opp->dst[i].tfrr);
         qemu_get_be32s(f, &opp->dst[i].pctp);
         qemu_get_be32s(f, &opp->dst[i].pcsr);
         openpic_load_IRQ_queue(f, &opp->dst[i].raised);
@@ -1100,7 +1099,6 @@ static void mpic_reset (void *opaque)
     /* Initialise IRQ destinations */
     for (i = 0; i < MAX_CPU; i++) {
         mpp->dst[i].pctp      = 0x0000000F;
-        mpp->dst[i].tfrr      = 0x00000000;
         memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
         mpp->dst[i].raised.next = -1;
         memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
@@ -1115,73 +1113,6 @@ static void mpic_reset (void *opaque)
     mpp->glbc = 0x00000000;
 }
 
-static void mpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
-                             unsigned len)
-{
-    openpic_t *mpp = opaque;
-    int idx, cpu;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
-    if (addr & 0xF)
-        return;
-    cpu = addr >> 12;
-    idx = (addr >> 6) & 0x3;
-    switch (addr & 0x30) {
-    case 0x00: /* gtccr */
-        break;
-    case 0x10: /* gtbcr */
-        if ((mpp->timers[idx].ticc & 0x80000000) != 0 &&
-            (val & 0x80000000) == 0 &&
-            (mpp->timers[idx].tibc & 0x80000000) != 0)
-            mpp->timers[idx].ticc &= ~0x80000000;
-        mpp->timers[idx].tibc = val;
-        break;
-    case 0x20: /* GTIVPR */
-        write_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx, val);
-        break;
-    case 0x30: /* GTIDR & TFRR */
-        if ((addr & 0xF0) == 0xF0)
-            mpp->dst[cpu].tfrr = val;
-        else
-            write_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx, val);
-        break;
-    }
-}
-
-static uint64_t mpic_timer_read(void *opaque, hwaddr addr, unsigned len)
-{
-    openpic_t *mpp = opaque;
-    uint32_t retval;
-    int idx, cpu;
-
-    DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
-    retval = 0xFFFFFFFF;
-    if (addr & 0xF)
-        return retval;
-    cpu = addr >> 12;
-    idx = (addr >> 6) & 0x3;
-    switch (addr & 0x30) {
-    case 0x00: /* gtccr */
-        retval = mpp->timers[idx].ticc;
-        break;
-    case 0x10: /* gtbcr */
-        retval = mpp->timers[idx].tibc;
-        break;
-    case 0x20: /* TIPV */
-        retval = read_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx);
-        break;
-    case 0x30: /* TIDR */
-        if ((addr &0xF0) == 0XF0)
-            retval = mpp->dst[cpu].tfrr;
-        else
-            retval = read_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx);
-        break;
-    }
-    DPRINTF("%s: => %08x\n", __func__, retval);
-
-    return retval;
-}
-
 static const MemoryRegionOps mpic_glb_ops = {
     .write = openpic_gbl_write,
     .read  = openpic_gbl_read,
@@ -1193,8 +1124,8 @@ static const MemoryRegionOps mpic_glb_ops = {
 };
 
 static const MemoryRegionOps mpic_tmr_ops = {
-    .write = mpic_timer_write,
-    .read  = mpic_timer_read,
+    .write = openpic_timer_write,
+    .read  = openpic_timer_read,
     .endianness = DEVICE_BIG_ENDIAN,
     .impl = {
         .min_access_size = 4,
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 19/40] openpic: combine openpic and mpic reset functions
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (17 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 18/40] openpic: merge mpic and openpic timer handling Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 20/40] openpic: unify memory api subregions Alexander Graf
                   ` (21 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The openpic and mpic reset handlers are almost identical. Combine
them and extract the differences into state variables.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |  103 +++++++++++++++++++++++----------------------------------
 1 files changed, 42 insertions(+), 61 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 80016a2..e94529b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -53,7 +53,6 @@
 #define MAX_IPI     4
 #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
 #define VID         0x03 /* MPIC version ID */
-#define VENI        0x00000000 /* Vendor ID */
 
 enum {
     IRQ_IPVP = 0,
@@ -125,6 +124,14 @@ enum {
 #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */
 #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
 
+#define FREP_NIRQ_SHIFT   16
+#define FREP_NCPU_SHIFT    8
+#define FREP_VID_SHIFT     0
+
+#define VID_REVISION_1_2   2
+
+#define VENI_GENERIC      0x00000000 /* Generic Vendor ID */
+
 enum mpic_ide_bits {
     IDR_EP     = 31,
     IDR_CI0     = 30,
@@ -208,6 +215,13 @@ typedef struct openpic_t {
 
     /* Behavior control */
     uint32_t flags;
+    uint32_t nb_irqs;
+    uint32_t vid;
+    uint32_t veni; /* Vendor identification register */
+    uint32_t spve_mask;
+    uint32_t tifr_reset;
+    uint32_t ipvp_reset;
+    uint32_t ide_reset;
 
     /* Sub-regions */
     MemoryRegion sub_io_mem[7];
@@ -215,8 +229,6 @@ typedef struct openpic_t {
     /* Global registers */
     uint32_t frep; /* Feature reporting register */
     uint32_t glbc; /* Global configuration register  */
-    uint32_t micr; /* MPIC interrupt configuration register */
-    uint32_t veni; /* Vendor identification register */
     uint32_t pint; /* Processor initialization register */
     uint32_t spve; /* Spurious vector register */
     uint32_t tifr; /* Timer frequency reporting register */
@@ -235,7 +247,6 @@ typedef struct openpic_t {
     int max_irq;
     int irq_ipi0;
     int irq_tim0;
-    void (*reset) (void *);
 } openpic_t;
 
 static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
@@ -412,17 +423,17 @@ static void openpic_reset (void *opaque)
 
     opp->glbc = 0x80000000;
     /* Initialise controller registers */
-    opp->frep = ((OPENPIC_EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID;
-    opp->veni = VENI;
+    opp->frep = ((opp->nb_irqs -1) << FREP_NIRQ_SHIFT) |
+                ((opp->nb_cpus -1) << FREP_NCPU_SHIFT) |
+                (opp->vid << FREP_VID_SHIFT);
+
     opp->pint = 0x00000000;
-    opp->spve = 0x000000FF;
-    opp->tifr = 0x003F7A00;
-    /* ? */
-    opp->micr = 0x00000000;
+    opp->spve = -1 & opp->spve_mask;
+    opp->tifr = opp->tifr_reset;
     /* Initialise IRQ sources */
     for (i = 0; i < opp->max_irq; i++) {
-        opp->src[i].ipvp = 0xA0000000;
-        opp->src[i].ide  = 0x00000000;
+        opp->src[i].ipvp = opp->ipvp_reset;
+        opp->src[i].ide  = opp->ide_reset;
     }
     /* Initialise IRQ destinations */
     for (i = 0; i < MAX_CPU; i++) {
@@ -499,9 +510,9 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
     case 0x1000: /* FREP */
         break;
     case 0x1020: /* GLBC */
-        if (val & 0x80000000 && opp->reset)
-            opp->reset(opp);
-        opp->glbc = val & ~0x80000000;
+        if (val & 0x80000000) {
+            openpic_reset(opp);
+        }
         break;
     case 0x1080: /* VENI */
         break;
@@ -530,7 +541,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
         }
         break;
     case 0x10E0: /* SPVE */
-        opp->spve = val & 0x000000FF;
+        opp->spve = val & opp->spve_mask;
         break;
     default:
         break;
@@ -912,9 +923,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
     openpic_t *opp = (openpic_t *)opaque;
     unsigned int i;
 
-    qemu_put_be32s(f, &opp->frep);
     qemu_put_be32s(f, &opp->glbc);
-    qemu_put_be32s(f, &opp->micr);
     qemu_put_be32s(f, &opp->veni);
     qemu_put_be32s(f, &opp->pint);
     qemu_put_be32s(f, &opp->spve);
@@ -964,9 +973,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
     if (version_id != 1)
         return -EINVAL;
 
-    qemu_get_be32s(f, &opp->frep);
     qemu_get_be32s(f, &opp->glbc);
-    qemu_get_be32s(f, &opp->micr);
     qemu_get_be32s(f, &opp->veni);
     qemu_get_be32s(f, &opp->pint);
     qemu_get_be32s(f, &opp->spve);
@@ -1043,6 +1050,11 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
 
     //    isu_base &= 0xFFFC0000;
     opp->nb_cpus = nb_cpus;
+    opp->nb_irqs = OPENPIC_EXT_IRQ;
+    opp->vid = VID;
+    opp->veni = VENI_GENERIC;
+    opp->spve_mask = 0xFF;
+    opp->tifr_reset = 0x003F7A00;
     opp->max_irq = OPENPIC_MAX_IRQ;
     opp->irq_ipi0 = OPENPIC_IRQ_IPI0;
     opp->irq_tim0 = OPENPIC_IRQ_TIM0;
@@ -1068,51 +1080,12 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
                     openpic_save, openpic_load, opp);
     qemu_register_reset(openpic_reset, opp);
 
-    opp->reset = openpic_reset;
-
     if (pmem)
         *pmem = &opp->mem;
 
     return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
 }
 
-static void mpic_reset (void *opaque)
-{
-    openpic_t *mpp = (openpic_t *)opaque;
-    int i;
-
-    mpp->glbc = 0x80000000;
-    /* Initialise controller registers */
-    mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8);
-    mpp->veni = VENI;
-    mpp->pint = 0x00000000;
-    mpp->spve = 0x0000FFFF;
-    /* Initialise IRQ sources */
-    for (i = 0; i < mpp->max_irq; i++) {
-        mpp->src[i].ipvp = 0x80800000;
-        mpp->src[i].ide  = 0x00000001;
-    }
-    /* Set IDE for IPIs to 0 so we don't get spurious interrupts */
-    for (i = mpp->irq_ipi0; i < (mpp->irq_ipi0 + MAX_IPI); i++) {
-        mpp->src[i].ide = 0;
-    }
-    /* Initialise IRQ destinations */
-    for (i = 0; i < MAX_CPU; i++) {
-        mpp->dst[i].pctp      = 0x0000000F;
-        memset(&mpp->dst[i].raised, 0, sizeof(IRQ_queue_t));
-        mpp->dst[i].raised.next = -1;
-        memset(&mpp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
-        mpp->dst[i].servicing.next = -1;
-    }
-    /* Initialise timers */
-    for (i = 0; i < MAX_TMR; i++) {
-        mpp->timers[i].ticc = 0x00000000;
-        mpp->timers[i].tibc = 0x80000000;
-    }
-    /* Go out of RESET state */
-    mpp->glbc = 0x00000000;
-}
-
 static const MemoryRegionOps mpic_glb_ops = {
     .write = openpic_gbl_write,
     .read  = openpic_gbl_read,
@@ -1185,6 +1158,15 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
     }
 
     mpp->nb_cpus = nb_cpus;
+    /* 12 external sources, 48 internal sources , 4 timer sources,
+       4 IPI sources, 4 messaging sources, and 8 Shared MSI sources */
+    mpp->nb_irqs = 80;
+    mpp->vid = VID_REVISION_1_2;
+    mpp->veni = VENI_GENERIC;
+    mpp->spve_mask = 0xFFFF;
+    mpp->tifr_reset = 0x00000000;
+    mpp->ipvp_reset = 0x80000000;
+    mpp->ide_reset = 0x00000001;
     mpp->max_irq = MPIC_MAX_IRQ;
     mpp->irq_ipi0 = MPIC_IPI_IRQ;
     mpp->irq_tim0 = MPIC_TMR_IRQ;
@@ -1195,10 +1177,9 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
 
     /* Enable critical interrupt support */
     mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
-    mpp->reset = mpic_reset;
 
     register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
-    qemu_register_reset(mpic_reset, mpp);
+    qemu_register_reset(openpic_reset, mpp);
 
     return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
 }
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 20/40] openpic: unify memory api subregions
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (18 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 19/40] openpic: combine openpic and mpic reset functions Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 21/40] openpic: remove unused type variable Alexander Graf
                   ` (20 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The only difference between the "openpic" and "mpic" memory api subregion
descriptors is the endianness. Unify them as openpic accessors with explicit
endianness markers in their names.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |  108 ++++++++++++++++++++++++++++++----------------------------
 1 files changed, 56 insertions(+), 52 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index e94529b..623c807 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -867,7 +867,7 @@ static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len)
     return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
 }
 
-static const MemoryRegionOps openpic_glb_ops = {
+static const MemoryRegionOps openpic_glb_ops_le = {
     .write = openpic_gbl_write,
     .read  = openpic_gbl_read,
     .endianness = DEVICE_LITTLE_ENDIAN,
@@ -877,7 +877,17 @@ static const MemoryRegionOps openpic_glb_ops = {
     },
 };
 
-static const MemoryRegionOps openpic_tmr_ops = {
+static const MemoryRegionOps openpic_glb_ops_be = {
+    .write = openpic_gbl_write,
+    .read  = openpic_gbl_read,
+    .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static const MemoryRegionOps openpic_tmr_ops_le = {
     .write = openpic_timer_write,
     .read  = openpic_timer_read,
     .endianness = DEVICE_LITTLE_ENDIAN,
@@ -887,7 +897,17 @@ static const MemoryRegionOps openpic_tmr_ops = {
     },
 };
 
-static const MemoryRegionOps openpic_cpu_ops = {
+static const MemoryRegionOps openpic_tmr_ops_be = {
+    .write = openpic_timer_write,
+    .read  = openpic_timer_read,
+    .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static const MemoryRegionOps openpic_cpu_ops_le = {
     .write = openpic_cpu_write,
     .read  = openpic_cpu_read,
     .endianness = DEVICE_LITTLE_ENDIAN,
@@ -897,7 +917,17 @@ static const MemoryRegionOps openpic_cpu_ops = {
     },
 };
 
-static const MemoryRegionOps openpic_src_ops = {
+static const MemoryRegionOps openpic_cpu_ops_be = {
+    .write = openpic_cpu_write,
+    .read  = openpic_cpu_read,
+    .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static const MemoryRegionOps openpic_src_ops_le = {
     .write = openpic_src_write,
     .read  = openpic_src_read,
     .endianness = DEVICE_LITTLE_ENDIAN,
@@ -907,6 +937,16 @@ static const MemoryRegionOps openpic_src_ops = {
     },
 };
 
+static const MemoryRegionOps openpic_src_ops_be = {
+    .write = openpic_src_write,
+    .read  = openpic_src_read,
+    .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
 static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
 {
     unsigned int i;
@@ -1026,10 +1066,14 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
         hwaddr      start_addr;
         ram_addr_t              size;
     } const list[] = {
-        {"glb", &openpic_glb_ops, OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
-        {"tmr", &openpic_tmr_ops, OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
-        {"src", &openpic_src_ops, OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
-        {"cpu", &openpic_cpu_ops, OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
+        {"glb", &openpic_glb_ops_le, OPENPIC_GLB_REG_START,
+                                     OPENPIC_GLB_REG_SIZE},
+        {"tmr", &openpic_tmr_ops_le, OPENPIC_TMR_REG_START,
+                                     OPENPIC_TMR_REG_SIZE},
+        {"src", &openpic_src_ops_le, OPENPIC_SRC_REG_START,
+                                     OPENPIC_SRC_REG_SIZE},
+        {"cpu", &openpic_cpu_ops_le, OPENPIC_CPU_REG_START,
+                                     OPENPIC_CPU_REG_SIZE},
     };
 
     /* XXX: for now, only one CPU is supported */
@@ -1086,46 +1130,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
     return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
 }
 
-static const MemoryRegionOps mpic_glb_ops = {
-    .write = openpic_gbl_write,
-    .read  = openpic_gbl_read,
-    .endianness = DEVICE_BIG_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
-    },
-};
-
-static const MemoryRegionOps mpic_tmr_ops = {
-    .write = openpic_timer_write,
-    .read  = openpic_timer_read,
-    .endianness = DEVICE_BIG_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
-    },
-};
-
-static const MemoryRegionOps mpic_cpu_ops = {
-    .write = openpic_cpu_write,
-    .read  = openpic_cpu_read,
-    .endianness = DEVICE_BIG_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
-    },
-};
-
-static const MemoryRegionOps mpic_irq_ops = {
-    .write = openpic_src_write,
-    .read  = openpic_src_read,
-    .endianness = DEVICE_BIG_ENDIAN,
-    .impl = {
-        .min_access_size = 4,
-        .max_access_size = 4,
-    },
-};
-
 qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
                      int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
 {
@@ -1137,10 +1141,10 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
         hwaddr      start_addr;
         ram_addr_t              size;
     } const list[] = {
-        {"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
-        {"tmr", &mpic_tmr_ops, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
-        {"src", &mpic_irq_ops, MPIC_SRC_REG_START, MPIC_SRC_REG_SIZE},
-        {"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
+        {"glb", &openpic_glb_ops_be, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
+        {"tmr", &openpic_tmr_ops_be, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
+        {"src", &openpic_src_ops_be, MPIC_SRC_REG_START, MPIC_SRC_REG_SIZE},
+        {"cpu", &openpic_cpu_ops_be, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
     };
 
     mpp = g_malloc0(sizeof(openpic_t));
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 21/40] openpic: remove unused type variable
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (19 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 20/40] openpic: unify memory api subregions Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 22/40] openpic: convert simple reg operations to builtin bitops Alexander Graf
                   ` (19 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The openpic source irqs are carrying around a type indicator that
is never accessed by anything. Remove it.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   27 ++-------------------------
 1 files changed, 2 insertions(+), 25 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 623c807..91e87b7 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -168,13 +168,6 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
                                        uint32_t val, int idx);
 
-enum {
-    IRQ_EXTERNAL = 0x01,
-    IRQ_INTERNAL = 0x02,
-    IRQ_TIMER    = 0x04,
-    IRQ_SPECIAL  = 0x08,
-};
-
 typedef struct IRQ_queue_t {
     uint32_t queue[BF_WIDTH(MAX_IRQ)];
     int next;
@@ -184,7 +177,6 @@ typedef struct IRQ_queue_t {
 typedef struct IRQ_src_t {
     uint32_t ipvp;  /* IRQ vector/priority register */
     uint32_t ide;   /* IRQ destination register */
-    int type;
     int last_cpu;
     int pending;    /* TRUE if IRQ is pending */
 } IRQ_src_t;
@@ -972,7 +964,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
     for (i = 0; i < opp->max_irq; i++) {
         qemu_put_be32s(f, &opp->src[i].ipvp);
         qemu_put_be32s(f, &opp->src[i].ide);
-        qemu_put_sbe32s(f, &opp->src[i].type);
         qemu_put_sbe32s(f, &opp->src[i].last_cpu);
         qemu_put_sbe32s(f, &opp->src[i].pending);
     }
@@ -1022,7 +1013,6 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
     for (i = 0; i < opp->max_irq; i++) {
         qemu_get_be32s(f, &opp->src[i].ipvp);
         qemu_get_be32s(f, &opp->src[i].ide);
-        qemu_get_sbe32s(f, &opp->src[i].type);
         qemu_get_sbe32s(f, &opp->src[i].last_cpu);
         qemu_get_sbe32s(f, &opp->src[i].pending);
     }
@@ -1059,7 +1049,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
                         qemu_irq **irqs, qemu_irq irq_out)
 {
     openpic_t *opp;
-    int i, m;
+    int i;
     struct {
         const char             *name;
         MemoryRegionOps const  *ops;
@@ -1102,20 +1092,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
     opp->max_irq = OPENPIC_MAX_IRQ;
     opp->irq_ipi0 = OPENPIC_IRQ_IPI0;
     opp->irq_tim0 = OPENPIC_IRQ_TIM0;
-    /* Set IRQ types */
-    for (i = 0; i < OPENPIC_EXT_IRQ; i++) {
-        opp->src[i].type = IRQ_EXTERNAL;
-    }
-    for (; i < OPENPIC_IRQ_TIM0; i++) {
-        opp->src[i].type = IRQ_SPECIAL;
-    }
-    m = OPENPIC_IRQ_IPI0;
-    for (; i < m; i++) {
-        opp->src[i].type = IRQ_TIMER;
-    }
-    for (; i < OPENPIC_MAX_IRQ; i++) {
-        opp->src[i].type = IRQ_INTERNAL;
-    }
+
     for (i = 0; i < nb_cpus; i++)
         opp->dst[i].irqs = irqs[i];
     opp->irq_out = irq_out;
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 22/40] openpic: convert simple reg operations to builtin bitops
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (20 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 21/40] openpic: remove unused type variable Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 23/40] openpic: rename openpic_t to OpenPICState Alexander Graf
                   ` (18 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The openpic code has its own bitmap code to access bits inside of a
bitmap. However, that is overkill when we simply want to check for a
bit inside of a uint32_t.

So instead, let's use normal bit masks and C builtin shifts and ands.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   67 +++++++++++++++++++++++++++++++--------------------------
 1 files changed, 36 insertions(+), 31 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 91e87b7..d2038d8 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -132,13 +132,12 @@ enum {
 
 #define VENI_GENERIC      0x00000000 /* Generic Vendor ID */
 
-enum mpic_ide_bits {
-    IDR_EP     = 31,
-    IDR_CI0     = 30,
-    IDR_CI1     = 29,
-    IDR_P1     = 1,
-    IDR_P0     = 0,
-};
+#define IDR_EP_SHIFT      31
+#define IDR_EP_MASK       (1 << IDR_EP_SHIFT)
+#define IDR_CI0_SHIFT     30
+#define IDR_CI1_SHIFT     29
+#define IDR_P1_SHIFT      1
+#define IDR_P0_SHIFT      0
 
 #define BF_WIDTH(_bits_) \
 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
@@ -181,13 +180,17 @@ typedef struct IRQ_src_t {
     int pending;    /* TRUE if IRQ is pending */
 } IRQ_src_t;
 
-enum IPVP_bits {
-    IPVP_MASK     = 31,
-    IPVP_ACTIVITY = 30,
-    IPVP_MODE     = 29,
-    IPVP_POLARITY = 23,
-    IPVP_SENSE    = 22,
-};
+#define IPVP_MASK_SHIFT       31
+#define IPVP_MASK_MASK        (1 << IPVP_MASK_SHIFT)
+#define IPVP_ACTIVITY_SHIFT   30
+#define IPVP_ACTIVITY_MASK    (1 << IPVP_ACTIVITY_SHIFT)
+#define IPVP_MODE_SHIFT       29
+#define IPVP_MODE_MASK        (1 << IPVP_MODE_SHIFT)
+#define IPVP_POLARITY_SHIFT   23
+#define IPVP_POLARITY_MASK    (1 << IPVP_POLARITY_SHIFT)
+#define IPVP_SENSE_SHIFT      22
+#define IPVP_SENSE_MASK       (1 << IPVP_SENSE_SHIFT)
+
 #define IPVP_PRIORITY_MASK     (0x1F << 16)
 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
 #define IPVP_VECTOR_MASK       ((1 << VECTOR_BITS) - 1)
@@ -310,7 +313,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
                 __func__, n_IRQ, n_CPU);
         return;
     }
-    set_bit(&src->ipvp, IPVP_ACTIVITY);
+    src->ipvp |= IPVP_ACTIVITY_MASK;
     IRQ_setbit(&dst->raised, n_IRQ);
     if (priority < dst->raised.priority) {
         /* An higher priority IRQ is already raised */
@@ -343,7 +346,7 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
         DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
         return;
     }
-    if (test_bit(&src->ipvp, IPVP_MASK)) {
+    if (src->ipvp & IPVP_MASK_MASK) {
         /* Interrupt source is disabled */
         DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
         return;
@@ -353,7 +356,7 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
         DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
         return;
     }
-    if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
+    if (src->ipvp & IPVP_ACTIVITY_MASK) {
         /* IRQ already active */
         DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ);
         return;
@@ -367,18 +370,19 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
     if (src->ide == (1 << src->last_cpu)) {
         /* Only one CPU is allowed to receive this IRQ */
         IRQ_local_pipe(opp, src->last_cpu, n_IRQ);
-    } else if (!test_bit(&src->ipvp, IPVP_MODE)) {
+    } else if (!(src->ipvp & IPVP_MODE_MASK)) {
         /* Directed delivery mode */
         for (i = 0; i < opp->nb_cpus; i++) {
-            if (test_bit(&src->ide, i))
+            if (src->ide & (1 << i)) {
                 IRQ_local_pipe(opp, i, n_IRQ);
+            }
         }
     } else {
         /* Distributed delivery mode */
         for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
             if (i == opp->nb_cpus)
                 i = 0;
-            if (test_bit(&src->ide, i)) {
+            if (src->ide & (1 << i)) {
                 IRQ_local_pipe(opp, i, n_IRQ);
                 src->last_cpu = i;
                 break;
@@ -395,11 +399,12 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
     src = &opp->src[n_IRQ];
     DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
             n_IRQ, level, src->ipvp);
-    if (test_bit(&src->ipvp, IPVP_SENSE)) {
+    if (src->ipvp & IPVP_SENSE_MASK) {
         /* level-sensitive irq */
         src->pending = level;
-        if (!level)
-            reset_bit(&src->ipvp, IPVP_ACTIVITY);
+        if (!level) {
+            src->ipvp &= ~IPVP_ACTIVITY_MASK;
+        }
     } else {
         /* edge-sensitive irq */
         if (level)
@@ -810,13 +815,13 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
             retval = IPVP_VECTOR(opp->spve);
         } else {
             src = &opp->src[n_IRQ];
-            if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
+            if (!(src->ipvp & IPVP_ACTIVITY_MASK) ||
                 !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
                 /* - Spurious level-sensitive IRQ
                  * - Priorities has been changed
                  *   and the pending IRQ isn't allowed anymore
                  */
-                reset_bit(&src->ipvp, IPVP_ACTIVITY);
+                src->ipvp &= ~IPVP_ACTIVITY_MASK;
                 retval = IPVP_VECTOR(opp->spve);
             } else {
                 /* IRQ enter servicing state */
@@ -825,20 +830,20 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
             }
             IRQ_resetbit(&dst->raised, n_IRQ);
             dst->raised.next = -1;
-            if (!test_bit(&src->ipvp, IPVP_SENSE)) {
+            if (!(src->ipvp & IPVP_SENSE_MASK)) {
                 /* edge-sensitive IRQ */
-                reset_bit(&src->ipvp, IPVP_ACTIVITY);
+                src->ipvp &= ~IPVP_ACTIVITY_MASK;
                 src->pending = 0;
             }
 
             if ((n_IRQ >= opp->irq_ipi0) &&  (n_IRQ < (opp->irq_ipi0 + MAX_IPI))) {
                 src->ide &= ~(1 << idx);
-                if (src->ide && !test_bit(&src->ipvp, IPVP_SENSE)) {
+                if (src->ide && !(src->ipvp & IPVP_SENSE_MASK)) {
                     /* trigger on CPUs that didn't know about it yet */
                     openpic_set_irq(opp, n_IRQ, 1);
                     openpic_set_irq(opp, n_IRQ, 0);
                     /* if all CPUs knew about it, set active bit again */
-                    set_bit(&src->ipvp, IPVP_ACTIVITY);
+                    src->ipvp |= IPVP_ACTIVITY_MASK;
                 }
             }
         }
@@ -1036,9 +1041,9 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
 
 static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
 {
-    int n_ci = IDR_CI0 - n_CPU;
+    int n_ci = IDR_CI0_SHIFT - n_CPU;
 
-    if ((opp->flags & OPENPIC_FLAG_IDE_CRIT) && test_bit(&src->ide, n_ci)) {
+    if ((opp->flags & OPENPIC_FLAG_IDE_CRIT) && (src->ide & (1 << n_ci))) {
         qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
     } else {
         qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]);
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 23/40] openpic: rename openpic_t to OpenPICState
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (21 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 22/40] openpic: convert simple reg operations to builtin bitops Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 24/40] openpic: remove irq_out Alexander Graf
                   ` (17 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

Rename the openpic_t struct to OpenPICState, so it adheres better to
the current coding style rules.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   68 +++++++++++++++++++++++++++++-----------------------------
 1 files changed, 34 insertions(+), 34 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index d2038d8..d5c2705 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -204,7 +204,7 @@ typedef struct IRQ_dst_t {
     qemu_irq *irqs;
 } IRQ_dst_t;
 
-typedef struct openpic_t {
+typedef struct OpenPICState {
     PCIDevice pci_dev;
     MemoryRegion mem;
 
@@ -242,9 +242,9 @@ typedef struct openpic_t {
     int max_irq;
     int irq_ipi0;
     int irq_tim0;
-} openpic_t;
+} OpenPICState;
 
-static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src);
+static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
 
 static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
 {
@@ -261,7 +261,7 @@ static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
     return test_bit(q->queue, n_IRQ);
 }
 
-static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
+static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
 {
     int next, i;
     int priority;
@@ -282,7 +282,7 @@ static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
     q->priority = priority;
 }
 
-static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
+static int IRQ_get_next(OpenPICState *opp, IRQ_queue_t *q)
 {
     if (q->next == -1) {
         /* XXX: optimize */
@@ -292,7 +292,7 @@ static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
     return q->next;
 }
 
-static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
+static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ)
 {
     IRQ_dst_t *dst;
     IRQ_src_t *src;
@@ -334,7 +334,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
 }
 
 /* update pic state because registers for n_IRQ have changed value */
-static void openpic_update_irq(openpic_t *opp, int n_IRQ)
+static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
 {
     IRQ_src_t *src;
     int i;
@@ -393,7 +393,7 @@ static void openpic_update_irq(openpic_t *opp, int n_IRQ)
 
 static void openpic_set_irq(void *opaque, int n_IRQ, int level)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     IRQ_src_t *src;
 
     src = &opp->src[n_IRQ];
@@ -415,7 +415,7 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
 
 static void openpic_reset (void *opaque)
 {
-    openpic_t *opp = (openpic_t *)opaque;
+    OpenPICState *opp = (OpenPICState *)opaque;
     int i;
 
     opp->glbc = 0x80000000;
@@ -450,17 +450,17 @@ static void openpic_reset (void *opaque)
     opp->glbc = 0x00000000;
 }
 
-static inline uint32_t read_IRQreg_ide(openpic_t *opp, int n_IRQ)
+static inline uint32_t read_IRQreg_ide(OpenPICState *opp, int n_IRQ)
 {
     return opp->src[n_IRQ].ide;
 }
 
-static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ)
+static inline uint32_t read_IRQreg_ipvp(OpenPICState *opp, int n_IRQ)
 {
     return opp->src[n_IRQ].ipvp;
 }
 
-static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val)
+static inline void write_IRQreg_ide(OpenPICState *opp, int n_IRQ, uint32_t val)
 {
     uint32_t tmp;
 
@@ -470,7 +470,7 @@ static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val)
     DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
 }
 
-static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
+static inline void write_IRQreg_ipvp(OpenPICState *opp, int n_IRQ, uint32_t val)
 {
     /* NOTE: not fully accurate for special IRQs, but simple and sufficient */
     /* ACTIVITY bit is read-only */
@@ -484,7 +484,7 @@ static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
 static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
                               unsigned len)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     IRQ_dst_t *dst;
     int idx;
 
@@ -547,7 +547,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
 
 static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     uint32_t retval;
 
     DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -599,10 +599,10 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len)
     return retval;
 }
 
-static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
+static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
                                 unsigned len)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     int idx;
 
     DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
@@ -635,9 +635,9 @@ static void openpic_timer_write(void *opaque, hwaddr addr, uint64_t val,
     }
 }
 
-static uint64_t openpic_timer_read(void *opaque, hwaddr addr, unsigned len)
+static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     uint32_t retval = -1;
     int idx;
 
@@ -675,7 +675,7 @@ out:
 static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
                               unsigned len)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     int idx;
 
     DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
@@ -694,7 +694,7 @@ static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val,
 
 static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     uint32_t retval;
     int idx;
 
@@ -719,7 +719,7 @@ static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
                                        uint32_t val, int idx)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     IRQ_src_t *src;
     IRQ_dst_t *dst;
     int s_IRQ, n_IRQ;
@@ -783,7 +783,7 @@ static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val,
 static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
                                           int idx)
 {
-    openpic_t *opp = opaque;
+    OpenPICState *opp = opaque;
     IRQ_src_t *src;
     IRQ_dst_t *dst;
     uint32_t retval;
@@ -885,8 +885,8 @@ static const MemoryRegionOps openpic_glb_ops_be = {
 };
 
 static const MemoryRegionOps openpic_tmr_ops_le = {
-    .write = openpic_timer_write,
-    .read  = openpic_timer_read,
+    .write = openpic_tmr_write,
+    .read  = openpic_tmr_read,
     .endianness = DEVICE_LITTLE_ENDIAN,
     .impl = {
         .min_access_size = 4,
@@ -895,8 +895,8 @@ static const MemoryRegionOps openpic_tmr_ops_le = {
 };
 
 static const MemoryRegionOps openpic_tmr_ops_be = {
-    .write = openpic_timer_write,
-    .read  = openpic_timer_read,
+    .write = openpic_tmr_write,
+    .read  = openpic_tmr_read,
     .endianness = DEVICE_BIG_ENDIAN,
     .impl = {
         .min_access_size = 4,
@@ -957,7 +957,7 @@ static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
 
 static void openpic_save(QEMUFile* f, void *opaque)
 {
-    openpic_t *opp = (openpic_t *)opaque;
+    OpenPICState *opp = (OpenPICState *)opaque;
     unsigned int i;
 
     qemu_put_be32s(f, &opp->glbc);
@@ -1003,7 +1003,7 @@ static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
 
 static int openpic_load(QEMUFile* f, void *opaque, int version_id)
 {
-    openpic_t *opp = (openpic_t *)opaque;
+    OpenPICState *opp = (OpenPICState *)opaque;
     unsigned int i;
 
     if (version_id != 1)
@@ -1039,7 +1039,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
     return pci_device_load(&opp->pci_dev, f);
 }
 
-static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
+static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
 {
     int n_ci = IDR_CI0_SHIFT - n_CPU;
 
@@ -1053,7 +1053,7 @@ static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
 qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
                         qemu_irq **irqs, qemu_irq irq_out)
 {
-    openpic_t *opp;
+    OpenPICState *opp;
     int i;
     struct {
         const char             *name;
@@ -1074,7 +1074,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
     /* XXX: for now, only one CPU is supported */
     if (nb_cpus != 1)
         return NULL;
-    opp = g_malloc0(sizeof(openpic_t));
+    opp = g_malloc0(sizeof(OpenPICState));
 
     memory_region_init(&opp->mem, "openpic", 0x40000);
 
@@ -1115,7 +1115,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
 qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
                      int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
 {
-    openpic_t    *mpp;
+    OpenPICState    *mpp;
     int           i;
     struct {
         const char             *name;
@@ -1129,7 +1129,7 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
         {"cpu", &openpic_cpu_ops_be, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
     };
 
-    mpp = g_malloc0(sizeof(openpic_t));
+    mpp = g_malloc0(sizeof(OpenPICState));
 
     memory_region_init(&mpp->mem, "mpic", 0x40000);
     memory_region_add_subregion(address_space, base, &mpp->mem);
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 24/40] openpic: remove irq_out
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (22 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 23/40] openpic: rename openpic_t to OpenPICState Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 25/40] openpic: convert to qdev Alexander Graf
                   ` (16 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The current openpic emulation contains half-ready code for bypass mode.
Remove it, so that when someone wants to finish it they can start from a
clean state.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c      |    8 ++------
 hw/openpic.h      |    4 ++--
 hw/ppc/e500.c     |    2 +-
 hw/ppc_newworld.c |    2 +-
 4 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index d5c2705..5116b3e 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -237,8 +237,6 @@ typedef struct OpenPICState {
         uint32_t ticc;  /* Global timer current count register */
         uint32_t tibc;  /* Global timer base count register */
     } timers[MAX_TMR];
-    /* IRQ out is used when in bypass mode (not implemented) */
-    qemu_irq irq_out;
     int max_irq;
     int irq_ipi0;
     int irq_tim0;
@@ -1051,7 +1049,7 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
 }
 
 qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
-                        qemu_irq **irqs, qemu_irq irq_out)
+                        qemu_irq **irqs)
 {
     OpenPICState *opp;
     int i;
@@ -1100,7 +1098,6 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
 
     for (i = 0; i < nb_cpus; i++)
         opp->dst[i].irqs = irqs[i];
-    opp->irq_out = irq_out;
 
     register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
                     openpic_save, openpic_load, opp);
@@ -1113,7 +1110,7 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
 }
 
 qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
-                     int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
+                     int nb_cpus, qemu_irq **irqs)
 {
     OpenPICState    *mpp;
     int           i;
@@ -1159,7 +1156,6 @@ qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
 
     for (i = 0; i < nb_cpus; i++)
         mpp->dst[i].irqs = irqs[i];
-    mpp->irq_out = irq_out;
 
     /* Enable critical interrupt support */
     mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
diff --git a/hw/openpic.h b/hw/openpic.h
index 1232d10..8a68f20 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -15,7 +15,7 @@ enum {
 #define OPENPIC_FLAG_IDE_CRIT    (1 << 0)
 
 qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
-                        qemu_irq **irqs, qemu_irq irq_out);
+                        qemu_irq **irqs);
 qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
-                     int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
+                     int nb_cpus, qemu_irq **irqs);
 #endif /* __OPENPIC_H__ */
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index f3e97d8..3f6d58c 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -493,7 +493,7 @@ void ppce500_init(PPCE500Params *params)
 
     /* MPIC */
     mpic = mpic_init(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
-                     smp_cpus, irqs, NULL);
+                     smp_cpus, irqs);
 
     if (!mpic) {
         cpu_abort(env, "MPIC failed to initialize\n");
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 664747e..b9c2cd8 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -320,7 +320,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
             exit(1);
         }
     }
-    pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs, NULL);
+    pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs);
     if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
         /* 970 gets a U3 bus */
         pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 25/40] openpic: convert to qdev
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (23 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 24/40] openpic: remove irq_out Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 20:32   ` Blue Swirl
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 26/40] openpic: make brr1 model specific Alexander Graf
                   ` (15 subsequent siblings)
  40 siblings, 1 reply; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

This patch converts the OpenPIC device to qdev. Along the way it
renames the "openpic" target to "raven" and the "mpic" target to
"fsl_mpic_20", to better reflect the actual models they implement.

This way we have a generic OpenPIC device now that can handle
different flavors of the OpenPIC specification.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c      |  278 ++++++++++++++++++++++++++---------------------------
 hw/openpic.h      |    8 +-
 hw/ppc/e500.c     |   24 ++++-
 hw/ppc_newworld.c |   25 +++++-
 4 files changed, 180 insertions(+), 155 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 5116b3e..591b291 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -37,6 +37,7 @@
 #include "ppc_mac.h"
 #include "pci.h"
 #include "openpic.h"
+#include "sysbus.h"
 
 //#define DEBUG_OPENPIC
 
@@ -54,30 +55,10 @@
 #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
 #define VID         0x03 /* MPIC version ID */
 
-enum {
-    IRQ_IPVP = 0,
-    IRQ_IDE,
-};
-
-/* OpenPIC */
-#define OPENPIC_MAX_CPU      2
-#define OPENPIC_MAX_IRQ     64
-#define OPENPIC_EXT_IRQ     48
-#define OPENPIC_MAX_TMR      MAX_TMR
-#define OPENPIC_MAX_IPI      MAX_IPI
-
-/* Interrupt definitions */
-#define OPENPIC_IRQ_FE     (OPENPIC_EXT_IRQ)     /* Internal functional IRQ */
-#define OPENPIC_IRQ_ERR    (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
-#define OPENPIC_IRQ_TIM0   (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
-#if OPENPIC_MAX_IPI > 0
-#define OPENPIC_IRQ_IPI0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
-#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
-#else
-#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
-#define OPENPIC_IRQ_MBX0   (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
-#endif
+/* OpenPIC capability flags */
+#define OPENPIC_FLAG_IDE_CRIT     (1 << 0)
 
+/* OpenPIC address map */
 #define OPENPIC_GLB_REG_START        0x0
 #define OPENPIC_GLB_REG_SIZE         0x10F0
 #define OPENPIC_TMR_REG_START        0x10F0
@@ -87,31 +68,37 @@ enum {
 #define OPENPIC_CPU_REG_START        0x20000
 #define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
 
-/* MPIC */
-#define MPIC_MAX_CPU      1
-#define MPIC_MAX_EXT     12
-#define MPIC_MAX_INT     64
-#define MPIC_MAX_IRQ     MAX_IRQ
+/* Raven */
+#define RAVEN_MAX_CPU      2
+#define RAVEN_MAX_EXT     48
+#define RAVEN_MAX_IRQ     64
+#define RAVEN_MAX_TMR      MAX_TMR
+#define RAVEN_MAX_IPI      MAX_IPI
+
+/* Interrupt definitions */
+#define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
+#define RAVEN_ERR_IRQ    (RAVEN_MAX_EXT + 1) /* Error IRQ */
+#define RAVEN_TMR_IRQ    (RAVEN_MAX_EXT + 2) /* First timer IRQ */
+#define RAVEN_IPI_IRQ    (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
+/* First doorbell IRQ */
+#define RAVEN_DBL_IRQ    (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
+
+/* FSL_MPIC_20 */
+#define FSL_MPIC_20_MAX_CPU      1
+#define FSL_MPIC_20_MAX_EXT     12
+#define FSL_MPIC_20_MAX_INT     64
+#define FSL_MPIC_20_MAX_IRQ     MAX_IRQ
 
 /* Interrupt definitions */
 /* IRQs, accessible through the IRQ region */
-#define MPIC_EXT_IRQ      0x00
-#define MPIC_INT_IRQ      0x10
-#define MPIC_MSG_IRQ      0xb0
-#define MPIC_MSI_IRQ      0xe0
+#define FSL_MPIC_20_EXT_IRQ      0x00
+#define FSL_MPIC_20_INT_IRQ      0x10
+#define FSL_MPIC_20_MSG_IRQ      0xb0
+#define FSL_MPIC_20_MSI_IRQ      0xe0
 /* These are available through separate regions, but
    for simplicity's sake mapped into the same number space */
-#define MPIC_TMR_IRQ      0x100
-#define MPIC_IPI_IRQ      0x104
-
-#define MPIC_GLB_REG_START        0x0
-#define MPIC_GLB_REG_SIZE         0x10F0
-#define MPIC_TMR_REG_START        0x10F0
-#define MPIC_TMR_REG_SIZE         0x220
-#define MPIC_SRC_REG_START        0x10000
-#define MPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
-#define MPIC_CPU_REG_START        0x20000
-#define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
+#define FSL_MPIC_20_TMR_IRQ      0x100
+#define FSL_MPIC_20_IPI_IRQ      0x104
 
 /*
  * Block Revision Register1 (BRR1): QEMU does not fully emulate
@@ -129,6 +116,7 @@ enum {
 #define FREP_VID_SHIFT     0
 
 #define VID_REVISION_1_2   2
+#define VID_REVISION_1_3   3
 
 #define VENI_GENERIC      0x00000000 /* Generic Vendor ID */
 
@@ -205,10 +193,11 @@ typedef struct IRQ_dst_t {
 } IRQ_dst_t;
 
 typedef struct OpenPICState {
-    PCIDevice pci_dev;
+    SysBusDevice busdev;
     MemoryRegion mem;
 
     /* Behavior control */
+    uint32_t model;
     uint32_t flags;
     uint32_t nb_irqs;
     uint32_t vid;
@@ -231,15 +220,15 @@ typedef struct OpenPICState {
     IRQ_src_t src[MAX_IRQ];
     /* Local registers per output pin */
     IRQ_dst_t dst[MAX_CPU];
-    int nb_cpus;
+    uint32_t nb_cpus;
     /* Timer registers */
     struct {
         uint32_t ticc;  /* Global timer current count register */
         uint32_t tibc;  /* Global timer base count register */
     } timers[MAX_TMR];
-    int max_irq;
-    int irq_ipi0;
-    int irq_tim0;
+    uint32_t max_irq;
+    uint32_t irq_ipi0;
+    uint32_t irq_tim0;
 } OpenPICState;
 
 static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
@@ -411,9 +400,9 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
     openpic_update_irq(opp, n_IRQ);
 }
 
-static void openpic_reset (void *opaque)
+static void openpic_reset(DeviceState *d)
 {
-    OpenPICState *opp = (OpenPICState *)opaque;
+    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d));
     int i;
 
     opp->glbc = 0x80000000;
@@ -506,7 +495,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
         break;
     case 0x1020: /* GLBC */
         if (val & 0x80000000) {
-            openpic_reset(opp);
+            openpic_reset(&opp->busdev.qdev);
         }
         break;
     case 0x1080: /* VENI */
@@ -971,7 +960,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
         qemu_put_sbe32s(f, &opp->src[i].pending);
     }
 
-    qemu_put_sbe32s(f, &opp->nb_cpus);
+    qemu_put_be32s(f, &opp->nb_cpus);
 
     for (i = 0; i < opp->nb_cpus; i++) {
         qemu_put_be32s(f, &opp->dst[i].pctp);
@@ -984,8 +973,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
         qemu_put_be32s(f, &opp->timers[i].ticc);
         qemu_put_be32s(f, &opp->timers[i].tibc);
     }
-
-    pci_device_save(&opp->pci_dev, f);
 }
 
 static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
@@ -1020,7 +1007,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
         qemu_get_sbe32s(f, &opp->src[i].pending);
     }
 
-    qemu_get_sbe32s(f, &opp->nb_cpus);
+    qemu_get_be32s(f, &opp->nb_cpus);
 
     for (i = 0; i < opp->nb_cpus; i++) {
         qemu_get_be32s(f, &opp->dst[i].pctp);
@@ -1034,7 +1021,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
         qemu_get_be32s(f, &opp->timers[i].tibc);
     }
 
-    return pci_device_load(&opp->pci_dev, f);
+    return 0;
 }
 
 static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
@@ -1048,17 +1035,18 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
     }
 }
 
-qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
-                        qemu_irq **irqs)
+struct memreg {
+    const char             *name;
+    MemoryRegionOps const  *ops;
+    hwaddr      start_addr;
+    ram_addr_t              size;
+};
+
+static int openpic_init(SysBusDevice *dev)
 {
-    OpenPICState *opp;
-    int i;
-    struct {
-        const char             *name;
-        MemoryRegionOps const  *ops;
-        hwaddr      start_addr;
-        ram_addr_t              size;
-    } const list[] = {
+    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev);
+    int i, j;
+    const struct memreg list_le[] = {
         {"glb", &openpic_glb_ops_le, OPENPIC_GLB_REG_START,
                                      OPENPIC_GLB_REG_SIZE},
         {"tmr", &openpic_tmr_ops_le, OPENPIC_TMR_REG_START,
@@ -1068,16 +1056,57 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
         {"cpu", &openpic_cpu_ops_le, OPENPIC_CPU_REG_START,
                                      OPENPIC_CPU_REG_SIZE},
     };
+    const struct memreg list_be[] = {
+        {"glb", &openpic_glb_ops_be, OPENPIC_GLB_REG_START,
+                                     OPENPIC_GLB_REG_SIZE},
+        {"tmr", &openpic_tmr_ops_be, OPENPIC_TMR_REG_START,
+                                     OPENPIC_TMR_REG_SIZE},
+        {"src", &openpic_src_ops_be, OPENPIC_SRC_REG_START,
+                                     OPENPIC_SRC_REG_SIZE},
+        {"cpu", &openpic_cpu_ops_be, OPENPIC_CPU_REG_START,
+                                     OPENPIC_CPU_REG_SIZE},
+    };
+    struct memreg const *list;
 
-    /* XXX: for now, only one CPU is supported */
-    if (nb_cpus != 1)
-        return NULL;
-    opp = g_malloc0(sizeof(OpenPICState));
+    switch (opp->model) {
+    case OPENPIC_MODEL_FSL_MPIC_20:
+    default:
+        opp->flags |= OPENPIC_FLAG_IDE_CRIT;
+        opp->nb_irqs = 80;
+        opp->vid = VID_REVISION_1_2;
+        opp->veni = VENI_GENERIC;
+        opp->spve_mask = 0xFFFF;
+        opp->tifr_reset = 0x00000000;
+        opp->ipvp_reset = 0x80000000;
+        opp->ide_reset = 0x00000001;
+        opp->max_irq = FSL_MPIC_20_MAX_IRQ;
+        opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ;
+        opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
+        list = list_be;
+        break;
+    case OPENPIC_MODEL_RAVEN:
+        opp->nb_irqs = RAVEN_MAX_EXT;
+        opp->vid = VID_REVISION_1_3;
+        opp->veni = VENI_GENERIC;
+        opp->spve_mask = 0xFF;
+        opp->tifr_reset = 0x003F7A00;
+        opp->ipvp_reset = 0xA0000000;
+        opp->ide_reset = 0x00000000;
+        opp->max_irq = RAVEN_MAX_IRQ;
+        opp->irq_ipi0 = RAVEN_IPI_IRQ;
+        opp->irq_tim0 = RAVEN_TMR_IRQ;
+        list = list_le;
+
+        /* Only UP supported today */
+        if (opp->nb_cpus != 1) {
+            return -EINVAL;
+        }
+        break;
+    }
 
     memory_region_init(&opp->mem, "openpic", 0x40000);
 
-    for (i = 0; i < ARRAY_SIZE(list); i++) {
-
+    for (i = 0; i < ARRAY_SIZE(list_le); i++) {
         memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,
                               list[i].name, list[i].size);
 
@@ -1085,83 +1114,48 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
                                     &opp->sub_io_mem[i]);
     }
 
-    //    isu_base &= 0xFFFC0000;
-    opp->nb_cpus = nb_cpus;
-    opp->nb_irqs = OPENPIC_EXT_IRQ;
-    opp->vid = VID;
-    opp->veni = VENI_GENERIC;
-    opp->spve_mask = 0xFF;
-    opp->tifr_reset = 0x003F7A00;
-    opp->max_irq = OPENPIC_MAX_IRQ;
-    opp->irq_ipi0 = OPENPIC_IRQ_IPI0;
-    opp->irq_tim0 = OPENPIC_IRQ_TIM0;
-
-    for (i = 0; i < nb_cpus; i++)
-        opp->dst[i].irqs = irqs[i];
-
-    register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
+    for (i = 0; i < opp->nb_cpus; i++) {
+        opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB);
+        for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
+            sysbus_init_irq(dev, &opp->dst[i].irqs[j]);
+        }
+    }
+
+    register_savevm(&opp->busdev.qdev, "openpic", 0, 2,
                     openpic_save, openpic_load, opp);
-    qemu_register_reset(openpic_reset, opp);
 
-    if (pmem)
-        *pmem = &opp->mem;
+    sysbus_init_mmio(dev, &opp->mem);
+    qdev_init_gpio_in(&dev->qdev, openpic_set_irq, opp->max_irq);
 
-    return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
+    return 0;
 }
 
-qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
-                     int nb_cpus, qemu_irq **irqs)
-{
-    OpenPICState    *mpp;
-    int           i;
-    struct {
-        const char             *name;
-        MemoryRegionOps const  *ops;
-        hwaddr      start_addr;
-        ram_addr_t              size;
-    } const list[] = {
-        {"glb", &openpic_glb_ops_be, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
-        {"tmr", &openpic_tmr_ops_be, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
-        {"src", &openpic_src_ops_be, MPIC_SRC_REG_START, MPIC_SRC_REG_SIZE},
-        {"cpu", &openpic_cpu_ops_be, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
-    };
-
-    mpp = g_malloc0(sizeof(OpenPICState));
-
-    memory_region_init(&mpp->mem, "mpic", 0x40000);
-    memory_region_add_subregion(address_space, base, &mpp->mem);
+static Property openpic_properties[] = {
+    DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20),
+    DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1),
+    DEFINE_PROP_END_OF_LIST(),
+};
 
-    for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
+static void openpic_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 
-        memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp,
-                              list[i].name, list[i].size);
+    k->init = openpic_init;
+    dc->props = openpic_properties;
+    dc->reset = openpic_reset;
+}
 
-        memory_region_add_subregion(&mpp->mem, list[i].start_addr,
-                                    &mpp->sub_io_mem[i]);
-    }
+static TypeInfo openpic_info = {
+    .name          = "openpic",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(OpenPICState),
+    .class_init    = openpic_class_init,
+};
 
-    mpp->nb_cpus = nb_cpus;
-    /* 12 external sources, 48 internal sources , 4 timer sources,
-       4 IPI sources, 4 messaging sources, and 8 Shared MSI sources */
-    mpp->nb_irqs = 80;
-    mpp->vid = VID_REVISION_1_2;
-    mpp->veni = VENI_GENERIC;
-    mpp->spve_mask = 0xFFFF;
-    mpp->tifr_reset = 0x00000000;
-    mpp->ipvp_reset = 0x80000000;
-    mpp->ide_reset = 0x00000001;
-    mpp->max_irq = MPIC_MAX_IRQ;
-    mpp->irq_ipi0 = MPIC_IPI_IRQ;
-    mpp->irq_tim0 = MPIC_TMR_IRQ;
-
-    for (i = 0; i < nb_cpus; i++)
-        mpp->dst[i].irqs = irqs[i];
-
-    /* Enable critical interrupt support */
-    mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
-
-    register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
-    qemu_register_reset(openpic_reset, mpp);
-
-    return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
+static void openpic_register_types(void)
+{
+    type_register_static(&openpic_info);
 }
+
+type_init(openpic_register_types)
diff --git a/hw/openpic.h b/hw/openpic.h
index 8a68f20..e226d7b 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -11,11 +11,7 @@ enum {
     OPENPIC_OUTPUT_NB,
 };
 
-/* OpenPIC capability flags */
-#define OPENPIC_FLAG_IDE_CRIT    (1 << 0)
+#define OPENPIC_MODEL_RAVEN       0
+#define OPENPIC_MODEL_FSL_MPIC_20 1
 
-qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
-                        qemu_irq **irqs);
-qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
-                     int nb_cpus, qemu_irq **irqs);
 #endif /* __OPENPIC_H__ */
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 3f6d58c..fa9b8ed 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -418,7 +418,7 @@ void ppce500_init(PPCE500Params *params)
     target_ulong dt_base = 0;
     target_ulong initrd_base = 0;
     target_long initrd_size=0;
-    int i=0;
+    int i = 0, j, k;
     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
     qemu_irq **irqs, *mpic;
     DeviceState *dev;
@@ -492,13 +492,27 @@ void ppce500_init(PPCE500Params *params)
                                 ccsr_addr_space);
 
     /* MPIC */
-    mpic = mpic_init(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
-                     smp_cpus, irqs);
+    mpic = g_new(qemu_irq, 256);
+    dev = qdev_create(NULL, "openpic");
+    qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
+    qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20);
+    qdev_init_nofail(dev);
+    s = sysbus_from_qdev(dev);
+
+    k = 0;
+    for (i = 0; i < smp_cpus; i++) {
+        for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
+            sysbus_connect_irq(s, k++, irqs[i][j]);
+        }
+    }
 
-    if (!mpic) {
-        cpu_abort(env, "MPIC failed to initialize\n");
+    for (i = 0; i < 256; i++) {
+        mpic[i] = qdev_get_gpio_in(dev, i);
     }
 
+    memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
+                                s->mmio[0].memory);
+
     /* Serial */
     if (serial_hds[0]) {
         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index b9c2cd8..8c2114e 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -67,6 +67,7 @@
 #include "hw/usb.h"
 #include "blockdev.h"
 #include "exec-memory.h"
+#include "sysbus.h"
 
 #define MAX_IDE_BUS 2
 #define CFG_ADDR 0xf0000510
@@ -141,7 +142,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
     char *filename;
     qemu_irq *pic, **openpic_irqs;
     MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
-    int linux_boot, i;
+    int linux_boot, i, j, k;
     MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
     hwaddr kernel_base, initrd_base, cmdline_base = 0;
     long kernel_size, initrd_size;
@@ -156,6 +157,8 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
     void *fw_cfg;
     void *dbdma;
     int machine_arch;
+    SysBusDevice *s;
+    DeviceState *dev;
 
     linux_boot = (kernel_filename != NULL);
 
@@ -320,7 +323,25 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
             exit(1);
         }
     }
-    pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs);
+
+    pic = g_new(qemu_irq, 64);
+
+    dev = qdev_create(NULL, "openpic");
+    qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN);
+    qdev_init_nofail(dev);
+    s = sysbus_from_qdev(dev);
+    pic_mem = s->mmio[0].memory;
+    k = 0;
+    for (i = 0; i < smp_cpus; i++) {
+        for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
+            sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
+        }
+    }
+
+    for (i = 0; i < 64; i++) {
+        pic[i] = qdev_get_gpio_in(dev, i);
+    }
+
     if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
         /* 970 gets a U3 bus */
         pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* Re: [Qemu-devel] [PATCH 25/40] openpic: convert to qdev
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 25/40] openpic: convert to qdev Alexander Graf
@ 2012-12-14 20:32   ` Blue Swirl
  2012-12-14 20:42     ` Alexander Graf
  0 siblings, 1 reply; 47+ messages in thread
From: Blue Swirl @ 2012-12-14 20:32 UTC (permalink / raw)
  To: Alexander Graf; +Cc: qemu-ppc@nongnu.org List, qemu-devel qemu-devel

On Fri, Dec 14, 2012 at 12:13 PM, Alexander Graf <agraf@suse.de> wrote:
> This patch converts the OpenPIC device to qdev. Along the way it
> renames the "openpic" target to "raven" and the "mpic" target to
> "fsl_mpic_20", to better reflect the actual models they implement.
>
> This way we have a generic OpenPIC device now that can handle
> different flavors of the OpenPIC specification.
>
> Signed-off-by: Alexander Graf <agraf@suse.de>
> ---
>  hw/openpic.c      |  278 ++++++++++++++++++++++++++---------------------------
>  hw/openpic.h      |    8 +-
>  hw/ppc/e500.c     |   24 ++++-
>  hw/ppc_newworld.c |   25 +++++-
>  4 files changed, 180 insertions(+), 155 deletions(-)
>
> diff --git a/hw/openpic.c b/hw/openpic.c
> index 5116b3e..591b291 100644
> --- a/hw/openpic.c
> +++ b/hw/openpic.c
> @@ -37,6 +37,7 @@
>  #include "ppc_mac.h"
>  #include "pci.h"
>  #include "openpic.h"
> +#include "sysbus.h"
>
>  //#define DEBUG_OPENPIC
>
> @@ -54,30 +55,10 @@
>  #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
>  #define VID         0x03 /* MPIC version ID */
>
> -enum {
> -    IRQ_IPVP = 0,
> -    IRQ_IDE,
> -};
> -
> -/* OpenPIC */
> -#define OPENPIC_MAX_CPU      2
> -#define OPENPIC_MAX_IRQ     64
> -#define OPENPIC_EXT_IRQ     48
> -#define OPENPIC_MAX_TMR      MAX_TMR
> -#define OPENPIC_MAX_IPI      MAX_IPI
> -
> -/* Interrupt definitions */
> -#define OPENPIC_IRQ_FE     (OPENPIC_EXT_IRQ)     /* Internal functional IRQ */
> -#define OPENPIC_IRQ_ERR    (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
> -#define OPENPIC_IRQ_TIM0   (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
> -#if OPENPIC_MAX_IPI > 0
> -#define OPENPIC_IRQ_IPI0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
> -#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
> -#else
> -#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
> -#define OPENPIC_IRQ_MBX0   (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
> -#endif
> +/* OpenPIC capability flags */
> +#define OPENPIC_FLAG_IDE_CRIT     (1 << 0)
>
> +/* OpenPIC address map */
>  #define OPENPIC_GLB_REG_START        0x0
>  #define OPENPIC_GLB_REG_SIZE         0x10F0
>  #define OPENPIC_TMR_REG_START        0x10F0
> @@ -87,31 +68,37 @@ enum {
>  #define OPENPIC_CPU_REG_START        0x20000
>  #define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>
> -/* MPIC */
> -#define MPIC_MAX_CPU      1
> -#define MPIC_MAX_EXT     12
> -#define MPIC_MAX_INT     64
> -#define MPIC_MAX_IRQ     MAX_IRQ
> +/* Raven */
> +#define RAVEN_MAX_CPU      2
> +#define RAVEN_MAX_EXT     48
> +#define RAVEN_MAX_IRQ     64
> +#define RAVEN_MAX_TMR      MAX_TMR
> +#define RAVEN_MAX_IPI      MAX_IPI
> +
> +/* Interrupt definitions */
> +#define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
> +#define RAVEN_ERR_IRQ    (RAVEN_MAX_EXT + 1) /* Error IRQ */
> +#define RAVEN_TMR_IRQ    (RAVEN_MAX_EXT + 2) /* First timer IRQ */
> +#define RAVEN_IPI_IRQ    (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
> +/* First doorbell IRQ */
> +#define RAVEN_DBL_IRQ    (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
> +
> +/* FSL_MPIC_20 */
> +#define FSL_MPIC_20_MAX_CPU      1
> +#define FSL_MPIC_20_MAX_EXT     12
> +#define FSL_MPIC_20_MAX_INT     64
> +#define FSL_MPIC_20_MAX_IRQ     MAX_IRQ
>
>  /* Interrupt definitions */
>  /* IRQs, accessible through the IRQ region */
> -#define MPIC_EXT_IRQ      0x00
> -#define MPIC_INT_IRQ      0x10
> -#define MPIC_MSG_IRQ      0xb0
> -#define MPIC_MSI_IRQ      0xe0
> +#define FSL_MPIC_20_EXT_IRQ      0x00
> +#define FSL_MPIC_20_INT_IRQ      0x10
> +#define FSL_MPIC_20_MSG_IRQ      0xb0
> +#define FSL_MPIC_20_MSI_IRQ      0xe0
>  /* These are available through separate regions, but
>     for simplicity's sake mapped into the same number space */
> -#define MPIC_TMR_IRQ      0x100
> -#define MPIC_IPI_IRQ      0x104
> -
> -#define MPIC_GLB_REG_START        0x0
> -#define MPIC_GLB_REG_SIZE         0x10F0
> -#define MPIC_TMR_REG_START        0x10F0
> -#define MPIC_TMR_REG_SIZE         0x220
> -#define MPIC_SRC_REG_START        0x10000
> -#define MPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
> -#define MPIC_CPU_REG_START        0x20000
> -#define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
> +#define FSL_MPIC_20_TMR_IRQ      0x100
> +#define FSL_MPIC_20_IPI_IRQ      0x104
>
>  /*
>   * Block Revision Register1 (BRR1): QEMU does not fully emulate
> @@ -129,6 +116,7 @@ enum {
>  #define FREP_VID_SHIFT     0
>
>  #define VID_REVISION_1_2   2
> +#define VID_REVISION_1_3   3
>
>  #define VENI_GENERIC      0x00000000 /* Generic Vendor ID */
>
> @@ -205,10 +193,11 @@ typedef struct IRQ_dst_t {
>  } IRQ_dst_t;
>
>  typedef struct OpenPICState {
> -    PCIDevice pci_dev;
> +    SysBusDevice busdev;
>      MemoryRegion mem;
>
>      /* Behavior control */
> +    uint32_t model;
>      uint32_t flags;
>      uint32_t nb_irqs;
>      uint32_t vid;
> @@ -231,15 +220,15 @@ typedef struct OpenPICState {
>      IRQ_src_t src[MAX_IRQ];
>      /* Local registers per output pin */
>      IRQ_dst_t dst[MAX_CPU];
> -    int nb_cpus;
> +    uint32_t nb_cpus;
>      /* Timer registers */
>      struct {
>          uint32_t ticc;  /* Global timer current count register */
>          uint32_t tibc;  /* Global timer base count register */
>      } timers[MAX_TMR];
> -    int max_irq;
> -    int irq_ipi0;
> -    int irq_tim0;
> +    uint32_t max_irq;
> +    uint32_t irq_ipi0;
> +    uint32_t irq_tim0;
>  } OpenPICState;
>
>  static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
> @@ -411,9 +400,9 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
>      openpic_update_irq(opp, n_IRQ);
>  }
>
> -static void openpic_reset (void *opaque)
> +static void openpic_reset(DeviceState *d)
>  {
> -    OpenPICState *opp = (OpenPICState *)opaque;
> +    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d));
>      int i;
>
>      opp->glbc = 0x80000000;
> @@ -506,7 +495,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
>          break;
>      case 0x1020: /* GLBC */
>          if (val & 0x80000000) {
> -            openpic_reset(opp);
> +            openpic_reset(&opp->busdev.qdev);
>          }
>          break;
>      case 0x1080: /* VENI */
> @@ -971,7 +960,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
>          qemu_put_sbe32s(f, &opp->src[i].pending);
>      }
>
> -    qemu_put_sbe32s(f, &opp->nb_cpus);
> +    qemu_put_be32s(f, &opp->nb_cpus);
>
>      for (i = 0; i < opp->nb_cpus; i++) {
>          qemu_put_be32s(f, &opp->dst[i].pctp);
> @@ -984,8 +973,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
>          qemu_put_be32s(f, &opp->timers[i].ticc);
>          qemu_put_be32s(f, &opp->timers[i].tibc);
>      }
> -
> -    pci_device_save(&opp->pci_dev, f);
>  }
>
>  static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
> @@ -1020,7 +1007,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
>          qemu_get_sbe32s(f, &opp->src[i].pending);
>      }
>
> -    qemu_get_sbe32s(f, &opp->nb_cpus);
> +    qemu_get_be32s(f, &opp->nb_cpus);
>
>      for (i = 0; i < opp->nb_cpus; i++) {
>          qemu_get_be32s(f, &opp->dst[i].pctp);
> @@ -1034,7 +1021,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
>          qemu_get_be32s(f, &opp->timers[i].tibc);
>      }
>
> -    return pci_device_load(&opp->pci_dev, f);
> +    return 0;
>  }
>
>  static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
> @@ -1048,17 +1035,18 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
>      }
>  }
>
> -qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
> -                        qemu_irq **irqs)
> +struct memreg {

Sorry for not noticing this earlier, but this should be MemReg with
also a typedef.

> +    const char             *name;
> +    MemoryRegionOps const  *ops;
> +    hwaddr      start_addr;
> +    ram_addr_t              size;
> +};
> +
> +static int openpic_init(SysBusDevice *dev)
>  {
> -    OpenPICState *opp;
> -    int i;
> -    struct {
> -        const char             *name;
> -        MemoryRegionOps const  *ops;
> -        hwaddr      start_addr;
> -        ram_addr_t              size;
> -    } const list[] = {
> +    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev);
> +    int i, j;
> +    const struct memreg list_le[] = {
>          {"glb", &openpic_glb_ops_le, OPENPIC_GLB_REG_START,
>                                       OPENPIC_GLB_REG_SIZE},
>          {"tmr", &openpic_tmr_ops_le, OPENPIC_TMR_REG_START,
> @@ -1068,16 +1056,57 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
>          {"cpu", &openpic_cpu_ops_le, OPENPIC_CPU_REG_START,
>                                       OPENPIC_CPU_REG_SIZE},
>      };
> +    const struct memreg list_be[] = {
> +        {"glb", &openpic_glb_ops_be, OPENPIC_GLB_REG_START,
> +                                     OPENPIC_GLB_REG_SIZE},
> +        {"tmr", &openpic_tmr_ops_be, OPENPIC_TMR_REG_START,
> +                                     OPENPIC_TMR_REG_SIZE},
> +        {"src", &openpic_src_ops_be, OPENPIC_SRC_REG_START,
> +                                     OPENPIC_SRC_REG_SIZE},
> +        {"cpu", &openpic_cpu_ops_be, OPENPIC_CPU_REG_START,
> +                                     OPENPIC_CPU_REG_SIZE},
> +    };
> +    struct memreg const *list;
>
> -    /* XXX: for now, only one CPU is supported */
> -    if (nb_cpus != 1)
> -        return NULL;
> -    opp = g_malloc0(sizeof(OpenPICState));
> +    switch (opp->model) {
> +    case OPENPIC_MODEL_FSL_MPIC_20:
> +    default:
> +        opp->flags |= OPENPIC_FLAG_IDE_CRIT;
> +        opp->nb_irqs = 80;
> +        opp->vid = VID_REVISION_1_2;
> +        opp->veni = VENI_GENERIC;
> +        opp->spve_mask = 0xFFFF;
> +        opp->tifr_reset = 0x00000000;
> +        opp->ipvp_reset = 0x80000000;
> +        opp->ide_reset = 0x00000001;
> +        opp->max_irq = FSL_MPIC_20_MAX_IRQ;
> +        opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ;
> +        opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
> +        list = list_be;
> +        break;
> +    case OPENPIC_MODEL_RAVEN:
> +        opp->nb_irqs = RAVEN_MAX_EXT;
> +        opp->vid = VID_REVISION_1_3;
> +        opp->veni = VENI_GENERIC;
> +        opp->spve_mask = 0xFF;
> +        opp->tifr_reset = 0x003F7A00;
> +        opp->ipvp_reset = 0xA0000000;
> +        opp->ide_reset = 0x00000000;
> +        opp->max_irq = RAVEN_MAX_IRQ;
> +        opp->irq_ipi0 = RAVEN_IPI_IRQ;
> +        opp->irq_tim0 = RAVEN_TMR_IRQ;
> +        list = list_le;
> +
> +        /* Only UP supported today */
> +        if (opp->nb_cpus != 1) {
> +            return -EINVAL;
> +        }
> +        break;
> +    }
>
>      memory_region_init(&opp->mem, "openpic", 0x40000);
>
> -    for (i = 0; i < ARRAY_SIZE(list); i++) {
> -
> +    for (i = 0; i < ARRAY_SIZE(list_le); i++) {
>          memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,
>                                list[i].name, list[i].size);
>
> @@ -1085,83 +1114,48 @@ qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
>                                      &opp->sub_io_mem[i]);
>      }
>
> -    //    isu_base &= 0xFFFC0000;
> -    opp->nb_cpus = nb_cpus;
> -    opp->nb_irqs = OPENPIC_EXT_IRQ;
> -    opp->vid = VID;
> -    opp->veni = VENI_GENERIC;
> -    opp->spve_mask = 0xFF;
> -    opp->tifr_reset = 0x003F7A00;
> -    opp->max_irq = OPENPIC_MAX_IRQ;
> -    opp->irq_ipi0 = OPENPIC_IRQ_IPI0;
> -    opp->irq_tim0 = OPENPIC_IRQ_TIM0;
> -
> -    for (i = 0; i < nb_cpus; i++)
> -        opp->dst[i].irqs = irqs[i];
> -
> -    register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
> +    for (i = 0; i < opp->nb_cpus; i++) {
> +        opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB);
> +        for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
> +            sysbus_init_irq(dev, &opp->dst[i].irqs[j]);
> +        }
> +    }
> +
> +    register_savevm(&opp->busdev.qdev, "openpic", 0, 2,
>                      openpic_save, openpic_load, opp);
> -    qemu_register_reset(openpic_reset, opp);
>
> -    if (pmem)
> -        *pmem = &opp->mem;
> +    sysbus_init_mmio(dev, &opp->mem);
> +    qdev_init_gpio_in(&dev->qdev, openpic_set_irq, opp->max_irq);
>
> -    return qemu_allocate_irqs(openpic_set_irq, opp, opp->max_irq);
> +    return 0;
>  }
>
> -qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
> -                     int nb_cpus, qemu_irq **irqs)
> -{
> -    OpenPICState    *mpp;
> -    int           i;
> -    struct {
> -        const char             *name;
> -        MemoryRegionOps const  *ops;
> -        hwaddr      start_addr;
> -        ram_addr_t              size;
> -    } const list[] = {
> -        {"glb", &openpic_glb_ops_be, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
> -        {"tmr", &openpic_tmr_ops_be, MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
> -        {"src", &openpic_src_ops_be, MPIC_SRC_REG_START, MPIC_SRC_REG_SIZE},
> -        {"cpu", &openpic_cpu_ops_be, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
> -    };
> -
> -    mpp = g_malloc0(sizeof(OpenPICState));
> -
> -    memory_region_init(&mpp->mem, "mpic", 0x40000);
> -    memory_region_add_subregion(address_space, base, &mpp->mem);
> +static Property openpic_properties[] = {
> +    DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20),
> +    DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
>
> -    for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
> +static void openpic_class_init(ObjectClass *klass, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(klass);
> +    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
>
> -        memory_region_init_io(&mpp->sub_io_mem[i], list[i].ops, mpp,
> -                              list[i].name, list[i].size);
> +    k->init = openpic_init;
> +    dc->props = openpic_properties;
> +    dc->reset = openpic_reset;
> +}
>
> -        memory_region_add_subregion(&mpp->mem, list[i].start_addr,
> -                                    &mpp->sub_io_mem[i]);
> -    }
> +static TypeInfo openpic_info = {
> +    .name          = "openpic",
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(OpenPICState),
> +    .class_init    = openpic_class_init,
> +};
>
> -    mpp->nb_cpus = nb_cpus;
> -    /* 12 external sources, 48 internal sources , 4 timer sources,
> -       4 IPI sources, 4 messaging sources, and 8 Shared MSI sources */
> -    mpp->nb_irqs = 80;
> -    mpp->vid = VID_REVISION_1_2;
> -    mpp->veni = VENI_GENERIC;
> -    mpp->spve_mask = 0xFFFF;
> -    mpp->tifr_reset = 0x00000000;
> -    mpp->ipvp_reset = 0x80000000;
> -    mpp->ide_reset = 0x00000001;
> -    mpp->max_irq = MPIC_MAX_IRQ;
> -    mpp->irq_ipi0 = MPIC_IPI_IRQ;
> -    mpp->irq_tim0 = MPIC_TMR_IRQ;
> -
> -    for (i = 0; i < nb_cpus; i++)
> -        mpp->dst[i].irqs = irqs[i];
> -
> -    /* Enable critical interrupt support */
> -    mpp->flags |= OPENPIC_FLAG_IDE_CRIT;
> -
> -    register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
> -    qemu_register_reset(openpic_reset, mpp);
> -
> -    return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
> +static void openpic_register_types(void)
> +{
> +    type_register_static(&openpic_info);
>  }
> +
> +type_init(openpic_register_types)
> diff --git a/hw/openpic.h b/hw/openpic.h
> index 8a68f20..e226d7b 100644
> --- a/hw/openpic.h
> +++ b/hw/openpic.h
> @@ -11,11 +11,7 @@ enum {
>      OPENPIC_OUTPUT_NB,
>  };
>
> -/* OpenPIC capability flags */
> -#define OPENPIC_FLAG_IDE_CRIT    (1 << 0)
> +#define OPENPIC_MODEL_RAVEN       0
> +#define OPENPIC_MODEL_FSL_MPIC_20 1
>
> -qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
> -                        qemu_irq **irqs);
> -qemu_irq *mpic_init (MemoryRegion *address_space, hwaddr base,
> -                     int nb_cpus, qemu_irq **irqs);
>  #endif /* __OPENPIC_H__ */
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 3f6d58c..fa9b8ed 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -418,7 +418,7 @@ void ppce500_init(PPCE500Params *params)
>      target_ulong dt_base = 0;
>      target_ulong initrd_base = 0;
>      target_long initrd_size=0;
> -    int i=0;
> +    int i = 0, j, k;
>      unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
>      qemu_irq **irqs, *mpic;
>      DeviceState *dev;
> @@ -492,13 +492,27 @@ void ppce500_init(PPCE500Params *params)
>                                  ccsr_addr_space);
>
>      /* MPIC */
> -    mpic = mpic_init(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
> -                     smp_cpus, irqs);
> +    mpic = g_new(qemu_irq, 256);
> +    dev = qdev_create(NULL, "openpic");
> +    qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
> +    qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20);
> +    qdev_init_nofail(dev);
> +    s = sysbus_from_qdev(dev);
> +
> +    k = 0;
> +    for (i = 0; i < smp_cpus; i++) {
> +        for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
> +            sysbus_connect_irq(s, k++, irqs[i][j]);
> +        }
> +    }
>
> -    if (!mpic) {
> -        cpu_abort(env, "MPIC failed to initialize\n");
> +    for (i = 0; i < 256; i++) {
> +        mpic[i] = qdev_get_gpio_in(dev, i);
>      }
>
> +    memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
> +                                s->mmio[0].memory);
> +
>      /* Serial */
>      if (serial_hds[0]) {
>          serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
> diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
> index b9c2cd8..8c2114e 100644
> --- a/hw/ppc_newworld.c
> +++ b/hw/ppc_newworld.c
> @@ -67,6 +67,7 @@
>  #include "hw/usb.h"
>  #include "blockdev.h"
>  #include "exec-memory.h"
> +#include "sysbus.h"
>
>  #define MAX_IDE_BUS 2
>  #define CFG_ADDR 0xf0000510
> @@ -141,7 +142,7 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
>      char *filename;
>      qemu_irq *pic, **openpic_irqs;
>      MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
> -    int linux_boot, i;
> +    int linux_boot, i, j, k;
>      MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
>      hwaddr kernel_base, initrd_base, cmdline_base = 0;
>      long kernel_size, initrd_size;
> @@ -156,6 +157,8 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
>      void *fw_cfg;
>      void *dbdma;
>      int machine_arch;
> +    SysBusDevice *s;
> +    DeviceState *dev;
>
>      linux_boot = (kernel_filename != NULL);
>
> @@ -320,7 +323,25 @@ static void ppc_core99_init(QEMUMachineInitArgs *args)
>              exit(1);
>          }
>      }
> -    pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs);
> +
> +    pic = g_new(qemu_irq, 64);
> +
> +    dev = qdev_create(NULL, "openpic");
> +    qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN);
> +    qdev_init_nofail(dev);
> +    s = sysbus_from_qdev(dev);
> +    pic_mem = s->mmio[0].memory;
> +    k = 0;
> +    for (i = 0; i < smp_cpus; i++) {
> +        for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
> +            sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
> +        }
> +    }
> +
> +    for (i = 0; i < 64; i++) {
> +        pic[i] = qdev_get_gpio_in(dev, i);
> +    }
> +
>      if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
>          /* 970 gets a U3 bus */
>          pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
> --
> 1.6.0.2
>
>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [Qemu-devel] [PATCH 25/40] openpic: convert to qdev
  2012-12-14 20:32   ` Blue Swirl
@ 2012-12-14 20:42     ` Alexander Graf
  2012-12-14 20:50       ` Blue Swirl
  0 siblings, 1 reply; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 20:42 UTC (permalink / raw)
  To: Blue Swirl; +Cc: qemu-ppc@nongnu.org List, qemu-devel qemu-devel


On 14.12.2012, at 21:32, Blue Swirl wrote:

> On Fri, Dec 14, 2012 at 12:13 PM, Alexander Graf <agraf@suse.de> wrote:
>> This patch converts the OpenPIC device to qdev. Along the way it
>> renames the "openpic" target to "raven" and the "mpic" target to
>> "fsl_mpic_20", to better reflect the actual models they implement.
>> 
>> This way we have a generic OpenPIC device now that can handle
>> different flavors of the OpenPIC specification.
>> 
>> Signed-off-by: Alexander Graf <agraf@suse.de>
>> ---
>> hw/openpic.c      |  278 ++++++++++++++++++++++++++---------------------------
>> hw/openpic.h      |    8 +-
>> hw/ppc/e500.c     |   24 ++++-
>> hw/ppc_newworld.c |   25 +++++-
>> 4 files changed, 180 insertions(+), 155 deletions(-)
>> 
>> diff --git a/hw/openpic.c b/hw/openpic.c
>> index 5116b3e..591b291 100644
>> --- a/hw/openpic.c
>> +++ b/hw/openpic.c
>> @@ -37,6 +37,7 @@
>> #include "ppc_mac.h"
>> #include "pci.h"
>> #include "openpic.h"
>> +#include "sysbus.h"
>> 
>> //#define DEBUG_OPENPIC
>> 
>> @@ -54,30 +55,10 @@
>> #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
>> #define VID         0x03 /* MPIC version ID */
>> 
>> -enum {
>> -    IRQ_IPVP = 0,
>> -    IRQ_IDE,
>> -};
>> -
>> -/* OpenPIC */
>> -#define OPENPIC_MAX_CPU      2
>> -#define OPENPIC_MAX_IRQ     64
>> -#define OPENPIC_EXT_IRQ     48
>> -#define OPENPIC_MAX_TMR      MAX_TMR
>> -#define OPENPIC_MAX_IPI      MAX_IPI
>> -
>> -/* Interrupt definitions */
>> -#define OPENPIC_IRQ_FE     (OPENPIC_EXT_IRQ)     /* Internal functional IRQ */
>> -#define OPENPIC_IRQ_ERR    (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
>> -#define OPENPIC_IRQ_TIM0   (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
>> -#if OPENPIC_MAX_IPI > 0
>> -#define OPENPIC_IRQ_IPI0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
>> -#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
>> -#else
>> -#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
>> -#define OPENPIC_IRQ_MBX0   (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
>> -#endif
>> +/* OpenPIC capability flags */
>> +#define OPENPIC_FLAG_IDE_CRIT     (1 << 0)
>> 
>> +/* OpenPIC address map */
>> #define OPENPIC_GLB_REG_START        0x0
>> #define OPENPIC_GLB_REG_SIZE         0x10F0
>> #define OPENPIC_TMR_REG_START        0x10F0
>> @@ -87,31 +68,37 @@ enum {
>> #define OPENPIC_CPU_REG_START        0x20000
>> #define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>> 
>> -/* MPIC */
>> -#define MPIC_MAX_CPU      1
>> -#define MPIC_MAX_EXT     12
>> -#define MPIC_MAX_INT     64
>> -#define MPIC_MAX_IRQ     MAX_IRQ
>> +/* Raven */
>> +#define RAVEN_MAX_CPU      2
>> +#define RAVEN_MAX_EXT     48
>> +#define RAVEN_MAX_IRQ     64
>> +#define RAVEN_MAX_TMR      MAX_TMR
>> +#define RAVEN_MAX_IPI      MAX_IPI
>> +
>> +/* Interrupt definitions */
>> +#define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
>> +#define RAVEN_ERR_IRQ    (RAVEN_MAX_EXT + 1) /* Error IRQ */
>> +#define RAVEN_TMR_IRQ    (RAVEN_MAX_EXT + 2) /* First timer IRQ */
>> +#define RAVEN_IPI_IRQ    (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
>> +/* First doorbell IRQ */
>> +#define RAVEN_DBL_IRQ    (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
>> +
>> +/* FSL_MPIC_20 */
>> +#define FSL_MPIC_20_MAX_CPU      1
>> +#define FSL_MPIC_20_MAX_EXT     12
>> +#define FSL_MPIC_20_MAX_INT     64
>> +#define FSL_MPIC_20_MAX_IRQ     MAX_IRQ
>> 
>> /* Interrupt definitions */
>> /* IRQs, accessible through the IRQ region */
>> -#define MPIC_EXT_IRQ      0x00
>> -#define MPIC_INT_IRQ      0x10
>> -#define MPIC_MSG_IRQ      0xb0
>> -#define MPIC_MSI_IRQ      0xe0
>> +#define FSL_MPIC_20_EXT_IRQ      0x00
>> +#define FSL_MPIC_20_INT_IRQ      0x10
>> +#define FSL_MPIC_20_MSG_IRQ      0xb0
>> +#define FSL_MPIC_20_MSI_IRQ      0xe0
>> /* These are available through separate regions, but
>>    for simplicity's sake mapped into the same number space */
>> -#define MPIC_TMR_IRQ      0x100
>> -#define MPIC_IPI_IRQ      0x104
>> -
>> -#define MPIC_GLB_REG_START        0x0
>> -#define MPIC_GLB_REG_SIZE         0x10F0
>> -#define MPIC_TMR_REG_START        0x10F0
>> -#define MPIC_TMR_REG_SIZE         0x220
>> -#define MPIC_SRC_REG_START        0x10000
>> -#define MPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
>> -#define MPIC_CPU_REG_START        0x20000
>> -#define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>> +#define FSL_MPIC_20_TMR_IRQ      0x100
>> +#define FSL_MPIC_20_IPI_IRQ      0x104
>> 
>> /*
>>  * Block Revision Register1 (BRR1): QEMU does not fully emulate
>> @@ -129,6 +116,7 @@ enum {
>> #define FREP_VID_SHIFT     0
>> 
>> #define VID_REVISION_1_2   2
>> +#define VID_REVISION_1_3   3
>> 
>> #define VENI_GENERIC      0x00000000 /* Generic Vendor ID */
>> 
>> @@ -205,10 +193,11 @@ typedef struct IRQ_dst_t {
>> } IRQ_dst_t;
>> 
>> typedef struct OpenPICState {
>> -    PCIDevice pci_dev;
>> +    SysBusDevice busdev;
>>     MemoryRegion mem;
>> 
>>     /* Behavior control */
>> +    uint32_t model;
>>     uint32_t flags;
>>     uint32_t nb_irqs;
>>     uint32_t vid;
>> @@ -231,15 +220,15 @@ typedef struct OpenPICState {
>>     IRQ_src_t src[MAX_IRQ];
>>     /* Local registers per output pin */
>>     IRQ_dst_t dst[MAX_CPU];
>> -    int nb_cpus;
>> +    uint32_t nb_cpus;
>>     /* Timer registers */
>>     struct {
>>         uint32_t ticc;  /* Global timer current count register */
>>         uint32_t tibc;  /* Global timer base count register */
>>     } timers[MAX_TMR];
>> -    int max_irq;
>> -    int irq_ipi0;
>> -    int irq_tim0;
>> +    uint32_t max_irq;
>> +    uint32_t irq_ipi0;
>> +    uint32_t irq_tim0;
>> } OpenPICState;
>> 
>> static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
>> @@ -411,9 +400,9 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
>>     openpic_update_irq(opp, n_IRQ);
>> }
>> 
>> -static void openpic_reset (void *opaque)
>> +static void openpic_reset(DeviceState *d)
>> {
>> -    OpenPICState *opp = (OpenPICState *)opaque;
>> +    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d));
>>     int i;
>> 
>>     opp->glbc = 0x80000000;
>> @@ -506,7 +495,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
>>         break;
>>     case 0x1020: /* GLBC */
>>         if (val & 0x80000000) {
>> -            openpic_reset(opp);
>> +            openpic_reset(&opp->busdev.qdev);
>>         }
>>         break;
>>     case 0x1080: /* VENI */
>> @@ -971,7 +960,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
>>         qemu_put_sbe32s(f, &opp->src[i].pending);
>>     }
>> 
>> -    qemu_put_sbe32s(f, &opp->nb_cpus);
>> +    qemu_put_be32s(f, &opp->nb_cpus);
>> 
>>     for (i = 0; i < opp->nb_cpus; i++) {
>>         qemu_put_be32s(f, &opp->dst[i].pctp);
>> @@ -984,8 +973,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
>>         qemu_put_be32s(f, &opp->timers[i].ticc);
>>         qemu_put_be32s(f, &opp->timers[i].tibc);
>>     }
>> -
>> -    pci_device_save(&opp->pci_dev, f);
>> }
>> 
>> static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
>> @@ -1020,7 +1007,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
>>         qemu_get_sbe32s(f, &opp->src[i].pending);
>>     }
>> 
>> -    qemu_get_sbe32s(f, &opp->nb_cpus);
>> +    qemu_get_be32s(f, &opp->nb_cpus);
>> 
>>     for (i = 0; i < opp->nb_cpus; i++) {
>>         qemu_get_be32s(f, &opp->dst[i].pctp);
>> @@ -1034,7 +1021,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
>>         qemu_get_be32s(f, &opp->timers[i].tibc);
>>     }
>> 
>> -    return pci_device_load(&opp->pci_dev, f);
>> +    return 0;
>> }
>> 
>> static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
>> @@ -1048,17 +1035,18 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
>>     }
>> }
>> 
>> -qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
>> -                        qemu_irq **irqs)
>> +struct memreg {
> 
> Sorry for not noticing this earlier, but this should be MemReg with
> also a typedef.

Ok, would you mind a follow-up patch?


Alex

^ permalink raw reply	[flat|nested] 47+ messages in thread

* Re: [Qemu-devel] [PATCH 25/40] openpic: convert to qdev
  2012-12-14 20:42     ` Alexander Graf
@ 2012-12-14 20:50       ` Blue Swirl
  0 siblings, 0 replies; 47+ messages in thread
From: Blue Swirl @ 2012-12-14 20:50 UTC (permalink / raw)
  To: Alexander Graf; +Cc: qemu-ppc@nongnu.org List, qemu-devel qemu-devel

On Fri, Dec 14, 2012 at 8:42 PM, Alexander Graf <agraf@suse.de> wrote:
>
> On 14.12.2012, at 21:32, Blue Swirl wrote:
>
>> On Fri, Dec 14, 2012 at 12:13 PM, Alexander Graf <agraf@suse.de> wrote:
>>> This patch converts the OpenPIC device to qdev. Along the way it
>>> renames the "openpic" target to "raven" and the "mpic" target to
>>> "fsl_mpic_20", to better reflect the actual models they implement.
>>>
>>> This way we have a generic OpenPIC device now that can handle
>>> different flavors of the OpenPIC specification.
>>>
>>> Signed-off-by: Alexander Graf <agraf@suse.de>
>>> ---
>>> hw/openpic.c      |  278 ++++++++++++++++++++++++++---------------------------
>>> hw/openpic.h      |    8 +-
>>> hw/ppc/e500.c     |   24 ++++-
>>> hw/ppc_newworld.c |   25 +++++-
>>> 4 files changed, 180 insertions(+), 155 deletions(-)
>>>
>>> diff --git a/hw/openpic.c b/hw/openpic.c
>>> index 5116b3e..591b291 100644
>>> --- a/hw/openpic.c
>>> +++ b/hw/openpic.c
>>> @@ -37,6 +37,7 @@
>>> #include "ppc_mac.h"
>>> #include "pci.h"
>>> #include "openpic.h"
>>> +#include "sysbus.h"
>>>
>>> //#define DEBUG_OPENPIC
>>>
>>> @@ -54,30 +55,10 @@
>>> #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
>>> #define VID         0x03 /* MPIC version ID */
>>>
>>> -enum {
>>> -    IRQ_IPVP = 0,
>>> -    IRQ_IDE,
>>> -};
>>> -
>>> -/* OpenPIC */
>>> -#define OPENPIC_MAX_CPU      2
>>> -#define OPENPIC_MAX_IRQ     64
>>> -#define OPENPIC_EXT_IRQ     48
>>> -#define OPENPIC_MAX_TMR      MAX_TMR
>>> -#define OPENPIC_MAX_IPI      MAX_IPI
>>> -
>>> -/* Interrupt definitions */
>>> -#define OPENPIC_IRQ_FE     (OPENPIC_EXT_IRQ)     /* Internal functional IRQ */
>>> -#define OPENPIC_IRQ_ERR    (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
>>> -#define OPENPIC_IRQ_TIM0   (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
>>> -#if OPENPIC_MAX_IPI > 0
>>> -#define OPENPIC_IRQ_IPI0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
>>> -#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
>>> -#else
>>> -#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
>>> -#define OPENPIC_IRQ_MBX0   (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
>>> -#endif
>>> +/* OpenPIC capability flags */
>>> +#define OPENPIC_FLAG_IDE_CRIT     (1 << 0)
>>>
>>> +/* OpenPIC address map */
>>> #define OPENPIC_GLB_REG_START        0x0
>>> #define OPENPIC_GLB_REG_SIZE         0x10F0
>>> #define OPENPIC_TMR_REG_START        0x10F0
>>> @@ -87,31 +68,37 @@ enum {
>>> #define OPENPIC_CPU_REG_START        0x20000
>>> #define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>>>
>>> -/* MPIC */
>>> -#define MPIC_MAX_CPU      1
>>> -#define MPIC_MAX_EXT     12
>>> -#define MPIC_MAX_INT     64
>>> -#define MPIC_MAX_IRQ     MAX_IRQ
>>> +/* Raven */
>>> +#define RAVEN_MAX_CPU      2
>>> +#define RAVEN_MAX_EXT     48
>>> +#define RAVEN_MAX_IRQ     64
>>> +#define RAVEN_MAX_TMR      MAX_TMR
>>> +#define RAVEN_MAX_IPI      MAX_IPI
>>> +
>>> +/* Interrupt definitions */
>>> +#define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
>>> +#define RAVEN_ERR_IRQ    (RAVEN_MAX_EXT + 1) /* Error IRQ */
>>> +#define RAVEN_TMR_IRQ    (RAVEN_MAX_EXT + 2) /* First timer IRQ */
>>> +#define RAVEN_IPI_IRQ    (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
>>> +/* First doorbell IRQ */
>>> +#define RAVEN_DBL_IRQ    (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
>>> +
>>> +/* FSL_MPIC_20 */
>>> +#define FSL_MPIC_20_MAX_CPU      1
>>> +#define FSL_MPIC_20_MAX_EXT     12
>>> +#define FSL_MPIC_20_MAX_INT     64
>>> +#define FSL_MPIC_20_MAX_IRQ     MAX_IRQ
>>>
>>> /* Interrupt definitions */
>>> /* IRQs, accessible through the IRQ region */
>>> -#define MPIC_EXT_IRQ      0x00
>>> -#define MPIC_INT_IRQ      0x10
>>> -#define MPIC_MSG_IRQ      0xb0
>>> -#define MPIC_MSI_IRQ      0xe0
>>> +#define FSL_MPIC_20_EXT_IRQ      0x00
>>> +#define FSL_MPIC_20_INT_IRQ      0x10
>>> +#define FSL_MPIC_20_MSG_IRQ      0xb0
>>> +#define FSL_MPIC_20_MSI_IRQ      0xe0
>>> /* These are available through separate regions, but
>>>    for simplicity's sake mapped into the same number space */
>>> -#define MPIC_TMR_IRQ      0x100
>>> -#define MPIC_IPI_IRQ      0x104
>>> -
>>> -#define MPIC_GLB_REG_START        0x0
>>> -#define MPIC_GLB_REG_SIZE         0x10F0
>>> -#define MPIC_TMR_REG_START        0x10F0
>>> -#define MPIC_TMR_REG_SIZE         0x220
>>> -#define MPIC_SRC_REG_START        0x10000
>>> -#define MPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
>>> -#define MPIC_CPU_REG_START        0x20000
>>> -#define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>>> +#define FSL_MPIC_20_TMR_IRQ      0x100
>>> +#define FSL_MPIC_20_IPI_IRQ      0x104
>>>
>>> /*
>>>  * Block Revision Register1 (BRR1): QEMU does not fully emulate
>>> @@ -129,6 +116,7 @@ enum {
>>> #define FREP_VID_SHIFT     0
>>>
>>> #define VID_REVISION_1_2   2
>>> +#define VID_REVISION_1_3   3
>>>
>>> #define VENI_GENERIC      0x00000000 /* Generic Vendor ID */
>>>
>>> @@ -205,10 +193,11 @@ typedef struct IRQ_dst_t {
>>> } IRQ_dst_t;
>>>
>>> typedef struct OpenPICState {
>>> -    PCIDevice pci_dev;
>>> +    SysBusDevice busdev;
>>>     MemoryRegion mem;
>>>
>>>     /* Behavior control */
>>> +    uint32_t model;
>>>     uint32_t flags;
>>>     uint32_t nb_irqs;
>>>     uint32_t vid;
>>> @@ -231,15 +220,15 @@ typedef struct OpenPICState {
>>>     IRQ_src_t src[MAX_IRQ];
>>>     /* Local registers per output pin */
>>>     IRQ_dst_t dst[MAX_CPU];
>>> -    int nb_cpus;
>>> +    uint32_t nb_cpus;
>>>     /* Timer registers */
>>>     struct {
>>>         uint32_t ticc;  /* Global timer current count register */
>>>         uint32_t tibc;  /* Global timer base count register */
>>>     } timers[MAX_TMR];
>>> -    int max_irq;
>>> -    int irq_ipi0;
>>> -    int irq_tim0;
>>> +    uint32_t max_irq;
>>> +    uint32_t irq_ipi0;
>>> +    uint32_t irq_tim0;
>>> } OpenPICState;
>>>
>>> static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
>>> @@ -411,9 +400,9 @@ static void openpic_set_irq(void *opaque, int n_IRQ, int level)
>>>     openpic_update_irq(opp, n_IRQ);
>>> }
>>>
>>> -static void openpic_reset (void *opaque)
>>> +static void openpic_reset(DeviceState *d)
>>> {
>>> -    OpenPICState *opp = (OpenPICState *)opaque;
>>> +    OpenPICState *opp = FROM_SYSBUS(typeof (*opp), sysbus_from_qdev(d));
>>>     int i;
>>>
>>>     opp->glbc = 0x80000000;
>>> @@ -506,7 +495,7 @@ static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val,
>>>         break;
>>>     case 0x1020: /* GLBC */
>>>         if (val & 0x80000000) {
>>> -            openpic_reset(opp);
>>> +            openpic_reset(&opp->busdev.qdev);
>>>         }
>>>         break;
>>>     case 0x1080: /* VENI */
>>> @@ -971,7 +960,7 @@ static void openpic_save(QEMUFile* f, void *opaque)
>>>         qemu_put_sbe32s(f, &opp->src[i].pending);
>>>     }
>>>
>>> -    qemu_put_sbe32s(f, &opp->nb_cpus);
>>> +    qemu_put_be32s(f, &opp->nb_cpus);
>>>
>>>     for (i = 0; i < opp->nb_cpus; i++) {
>>>         qemu_put_be32s(f, &opp->dst[i].pctp);
>>> @@ -984,8 +973,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
>>>         qemu_put_be32s(f, &opp->timers[i].ticc);
>>>         qemu_put_be32s(f, &opp->timers[i].tibc);
>>>     }
>>> -
>>> -    pci_device_save(&opp->pci_dev, f);
>>> }
>>>
>>> static void openpic_load_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
>>> @@ -1020,7 +1007,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
>>>         qemu_get_sbe32s(f, &opp->src[i].pending);
>>>     }
>>>
>>> -    qemu_get_sbe32s(f, &opp->nb_cpus);
>>> +    qemu_get_be32s(f, &opp->nb_cpus);
>>>
>>>     for (i = 0; i < opp->nb_cpus; i++) {
>>>         qemu_get_be32s(f, &opp->dst[i].pctp);
>>> @@ -1034,7 +1021,7 @@ static int openpic_load(QEMUFile* f, void *opaque, int version_id)
>>>         qemu_get_be32s(f, &opp->timers[i].tibc);
>>>     }
>>>
>>> -    return pci_device_load(&opp->pci_dev, f);
>>> +    return 0;
>>> }
>>>
>>> static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
>>> @@ -1048,17 +1035,18 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
>>>     }
>>> }
>>>
>>> -qemu_irq *openpic_init (MemoryRegion **pmem, int nb_cpus,
>>> -                        qemu_irq **irqs)
>>> +struct memreg {
>>
>> Sorry for not noticing this earlier, but this should be MemReg with
>> also a typedef.
>
> Ok, would you mind a follow-up patch?

OK.

>
>
> Alex
>

^ permalink raw reply	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 26/40] openpic: make brr1 model specific
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (24 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 25/40] openpic: convert to qdev Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 27/40] openpic: add Shared MSI support Alexander Graf
                   ` (14 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

Now that we can properly distinguish between openpic model differences,
let's move brr1 out of the raven code path.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 591b291..5bf16ea 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -206,6 +206,7 @@ typedef struct OpenPICState {
     uint32_t tifr_reset;
     uint32_t ipvp_reset;
     uint32_t ide_reset;
+    uint32_t brr1;
 
     /* Sub-regions */
     MemoryRegion sub_io_mem[7];
@@ -784,7 +785,7 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
     addr &= 0xFF0;
     switch (addr) {
     case 0x00: /* Block Revision Register1 (BRR1) */
-        retval = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
+        retval = opp->brr1;
         break;
     case 0x80: /* PCTP */
         retval = dst->pctp;
@@ -1082,6 +1083,7 @@ static int openpic_init(SysBusDevice *dev)
         opp->max_irq = FSL_MPIC_20_MAX_IRQ;
         opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ;
         opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
+        opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
         list = list_be;
         break;
     case OPENPIC_MODEL_RAVEN:
@@ -1095,6 +1097,7 @@ static int openpic_init(SysBusDevice *dev)
         opp->max_irq = RAVEN_MAX_IRQ;
         opp->irq_ipi0 = RAVEN_IPI_IRQ;
         opp->irq_tim0 = RAVEN_TMR_IRQ;
+        opp->brr1 = -1;
         list = list_le;
 
         /* Only UP supported today */
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 27/40] openpic: add Shared MSI support
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (25 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 26/40] openpic: make brr1 model specific Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 28/40] PPC: e500: Add " Alexander Graf
                   ` (13 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The OpenPIC allows MSI access through shared MSI registers. Implement
them for the MPC8544 MPIC, so we can support MSIs.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |  150 ++++++++++++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 130 insertions(+), 20 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 5bf16ea..4bea1e7 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -38,6 +38,7 @@
 #include "pci.h"
 #include "openpic.h"
 #include "sysbus.h"
+#include "msi.h"
 
 //#define DEBUG_OPENPIC
 
@@ -52,6 +53,7 @@
 #define MAX_TMR     4
 #define VECTOR_BITS 8
 #define MAX_IPI     4
+#define MAX_MSI     8
 #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
 #define VID         0x03 /* MPIC version ID */
 
@@ -63,6 +65,8 @@
 #define OPENPIC_GLB_REG_SIZE         0x10F0
 #define OPENPIC_TMR_REG_START        0x10F0
 #define OPENPIC_TMR_REG_SIZE         0x220
+#define OPENPIC_MSI_REG_START        0x1600
+#define OPENPIC_MSI_REG_SIZE         0x200
 #define OPENPIC_SRC_REG_START        0x10000
 #define OPENPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
 #define OPENPIC_CPU_REG_START        0x20000
@@ -127,6 +131,12 @@
 #define IDR_P1_SHIFT      1
 #define IDR_P0_SHIFT      0
 
+#define MSIIR_OFFSET       0x140
+#define MSIIR_SRS_SHIFT    29
+#define MSIIR_SRS_MASK     (0x7 << MSIIR_SRS_SHIFT)
+#define MSIIR_IBS_SHIFT    24
+#define MSIIR_IBS_MASK     (0x1f << MSIIR_IBS_SHIFT)
+
 #define BF_WIDTH(_bits_) \
 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
 
@@ -209,7 +219,7 @@ typedef struct OpenPICState {
     uint32_t brr1;
 
     /* Sub-regions */
-    MemoryRegion sub_io_mem[7];
+    MemoryRegion sub_io_mem[5];
 
     /* Global registers */
     uint32_t frep; /* Feature reporting register */
@@ -227,9 +237,14 @@ typedef struct OpenPICState {
         uint32_t ticc;  /* Global timer current count register */
         uint32_t tibc;  /* Global timer base count register */
     } timers[MAX_TMR];
+    /* Shared MSI registers */
+    struct {
+        uint32_t msir;   /* Shared Message Signaled Interrupt Register */
+    } msi[MAX_MSI];
     uint32_t max_irq;
     uint32_t irq_ipi0;
     uint32_t irq_tim0;
+    uint32_t irq_msi;
 } OpenPICState;
 
 static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
@@ -704,6 +719,68 @@ static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
     return retval;
 }
 
+static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val,
+                              unsigned size)
+{
+    OpenPICState *opp = opaque;
+    int idx = opp->irq_msi;
+    int srs, ibs;
+
+    DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
+    if (addr & 0xF) {
+        return;
+    }
+
+    switch (addr) {
+    case MSIIR_OFFSET:
+        srs = val >> MSIIR_SRS_SHIFT;
+        idx += srs;
+        ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
+        opp->msi[srs].msir |= 1 << ibs;
+        openpic_set_irq(opp, idx, 1);
+        break;
+    default:
+        /* most registers are read-only, thus ignored */
+        break;
+    }
+}
+
+static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
+{
+    OpenPICState *opp = opaque;
+    uint64_t r = 0;
+    int i, srs;
+
+    DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
+    if (addr & 0xF) {
+        return -1;
+    }
+
+    srs = addr >> 4;
+
+    switch (addr) {
+    case 0x00:
+    case 0x10:
+    case 0x20:
+    case 0x30:
+    case 0x40:
+    case 0x50:
+    case 0x60:
+    case 0x70: /* MSIRs */
+        r = opp->msi[srs].msir;
+        /* Clear on read */
+        opp->msi[srs].msir = 0;
+        break;
+    case 0x120: /* MSISR */
+        for (i = 0; i < MAX_MSI; i++) {
+            r |= (opp->msi[i].msir ? 1 : 0) << i;
+        }
+        break;
+    }
+
+    return r;
+}
+
 static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
                                        uint32_t val, int idx)
 {
@@ -932,6 +1009,26 @@ static const MemoryRegionOps openpic_src_ops_be = {
     },
 };
 
+static const MemoryRegionOps openpic_msi_ops_le = {
+    .read = openpic_msi_read,
+    .write = openpic_msi_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static const MemoryRegionOps openpic_msi_ops_be = {
+    .read = openpic_msi_read,
+    .write = openpic_msi_write,
+    .endianness = DEVICE_BIG_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
 static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
 {
     unsigned int i;
@@ -1039,6 +1136,7 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
 struct memreg {
     const char             *name;
     MemoryRegionOps const  *ops;
+    bool                   map;
     hwaddr      start_addr;
     ram_addr_t              size;
 };
@@ -1047,27 +1145,31 @@ static int openpic_init(SysBusDevice *dev)
 {
     OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev);
     int i, j;
-    const struct memreg list_le[] = {
-        {"glb", &openpic_glb_ops_le, OPENPIC_GLB_REG_START,
-                                     OPENPIC_GLB_REG_SIZE},
-        {"tmr", &openpic_tmr_ops_le, OPENPIC_TMR_REG_START,
-                                     OPENPIC_TMR_REG_SIZE},
-        {"src", &openpic_src_ops_le, OPENPIC_SRC_REG_START,
-                                     OPENPIC_SRC_REG_SIZE},
-        {"cpu", &openpic_cpu_ops_le, OPENPIC_CPU_REG_START,
-                                     OPENPIC_CPU_REG_SIZE},
+    struct memreg list_le[] = {
+        {"glb", &openpic_glb_ops_le, true,
+                OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
+        {"tmr", &openpic_tmr_ops_le, true,
+                OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
+        {"msi", &openpic_msi_ops_le, true,
+                OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
+        {"src", &openpic_src_ops_le, true,
+                OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
+        {"cpu", &openpic_cpu_ops_le, true,
+                OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
     };
-    const struct memreg list_be[] = {
-        {"glb", &openpic_glb_ops_be, OPENPIC_GLB_REG_START,
-                                     OPENPIC_GLB_REG_SIZE},
-        {"tmr", &openpic_tmr_ops_be, OPENPIC_TMR_REG_START,
-                                     OPENPIC_TMR_REG_SIZE},
-        {"src", &openpic_src_ops_be, OPENPIC_SRC_REG_START,
-                                     OPENPIC_SRC_REG_SIZE},
-        {"cpu", &openpic_cpu_ops_be, OPENPIC_CPU_REG_START,
-                                     OPENPIC_CPU_REG_SIZE},
+    struct memreg list_be[] = {
+        {"glb", &openpic_glb_ops_be, true,
+                OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
+        {"tmr", &openpic_tmr_ops_be, true,
+                OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
+        {"msi", &openpic_msi_ops_be, true,
+                OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
+        {"src", &openpic_src_ops_be, true,
+                OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
+        {"cpu", &openpic_cpu_ops_be, true,
+                OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
     };
-    struct memreg const *list;
+    struct memreg *list;
 
     switch (opp->model) {
     case OPENPIC_MODEL_FSL_MPIC_20:
@@ -1083,7 +1185,9 @@ static int openpic_init(SysBusDevice *dev)
         opp->max_irq = FSL_MPIC_20_MAX_IRQ;
         opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ;
         opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
+        opp->irq_msi = FSL_MPIC_20_MSI_IRQ;
         opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
+        msi_supported = true;
         list = list_be;
         break;
     case OPENPIC_MODEL_RAVEN:
@@ -1099,6 +1203,8 @@ static int openpic_init(SysBusDevice *dev)
         opp->irq_tim0 = RAVEN_TMR_IRQ;
         opp->brr1 = -1;
         list = list_le;
+        /* Don't map MSI region */
+        list[2].map = false;
 
         /* Only UP supported today */
         if (opp->nb_cpus != 1) {
@@ -1110,6 +1216,10 @@ static int openpic_init(SysBusDevice *dev)
     memory_region_init(&opp->mem, "openpic", 0x40000);
 
     for (i = 0; i < ARRAY_SIZE(list_le); i++) {
+        if (!list[i].map) {
+            continue;
+        }
+
         memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,
                               list[i].name, list[i].size);
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 28/40] PPC: e500: Add MSI support
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (26 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 27/40] openpic: add Shared MSI support Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 29/40] PPC: e500: Declare pci bridge as bridge Alexander Graf
                   ` (12 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

Now that our interrupt controller supports MSIs, let's expose that feature
to the guest through the device tree!

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/e500.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index fa9b8ed..1034f93 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -48,6 +48,7 @@
 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
+#define MPC8544_MSI_REGS_OFFSET   0x41600ULL
 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
@@ -127,8 +128,10 @@ static int ppce500_load_device_tree(CPUPPCState *env,
     char soc[128];
     char mpic[128];
     uint32_t mpic_ph;
+    uint32_t msi_ph;
     char gutil[128];
     char pci[128];
+    char msi[128];
     uint32_t pci_map[7 * 8];
     uint32_t pci_ranges[14] =
         {
@@ -300,6 +303,25 @@ static int ppce500_load_device_tree(CPUPPCState *env,
     qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 
+    snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
+    qemu_devtree_add_subnode(fdt, msi);
+    qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
+    qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
+    msi_ph = qemu_devtree_alloc_phandle(fdt);
+    qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
+    qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
+    qemu_devtree_setprop_cells(fdt, msi, "interrupts",
+        0xe0, 0x0,
+        0xe1, 0x0,
+        0xe2, 0x0,
+        0xe3, 0x0,
+        0xe4, 0x0,
+        0xe5, 0x0,
+        0xe6, 0x0,
+        0xe7, 0x0);
+    qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
+    qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
+
     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
     qemu_devtree_add_subnode(fdt, pci);
     qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
@@ -315,6 +337,7 @@ static int ppce500_load_device_tree(CPUPPCState *env,
     for (i = 0; i < 14; i++) {
         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
     }
+    qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
     qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
     qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
                                MPC8544_PCI_REGS_BASE, 0, 0x1000);
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 29/40] PPC: e500: Declare pci bridge as bridge
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (27 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 28/40] PPC: e500: Add " Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 30/40] MSI-X: Fix endianness Alexander Graf
                   ` (11 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The new PCI host bridge device needs to identify itself as PCI host bridge.
Declare it as such.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_pci.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 54c72b4..e534341 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -330,9 +330,15 @@ static int e500_pcihost_bridge_initfn(PCIDevice *d)
     PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
                                   "/e500-ccsr"));
 
+    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
+    d->config[PCI_HEADER_TYPE] =
+        (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
+        PCI_HEADER_TYPE_BRIDGE;
+
     memory_region_init_alias(&b->bar0, "e500-pci-bar0", &ccsr->ccsr_space,
                              0, int128_get64(ccsr->ccsr_space.size));
     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
+
     return 0;
 }
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 30/40] MSI-X: Fix endianness
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (28 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 29/40] PPC: e500: Declare pci bridge as bridge Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 31/40] openpic: fix minor coding style issues Alexander Graf
                   ` (10 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The MSI-X vector tables are usually stored in little endian in memory,
so let's mark the accessors as such.

This fixes MSI-X on e500 for me.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/msix.c |    6 ++----
 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/msix.c b/hw/msix.c
index 136ef09..b57ae60 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -180,8 +180,7 @@ static void msix_table_mmio_write(void *opaque, hwaddr addr,
 static const MemoryRegionOps msix_table_mmio_ops = {
     .read = msix_table_mmio_read,
     .write = msix_table_mmio_write,
-    /* TODO: MSIX should be LITTLE_ENDIAN. */
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
     .valid = {
         .min_access_size = 4,
         .max_access_size = 4,
@@ -198,8 +197,7 @@ static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
 
 static const MemoryRegionOps msix_pba_mmio_ops = {
     .read = msix_pba_mmio_read,
-    /* TODO: MSIX should be LITTLE_ENDIAN. */
-    .endianness = DEVICE_NATIVE_ENDIAN,
+    .endianness = DEVICE_LITTLE_ENDIAN,
     .valid = {
         .min_access_size = 4,
         .max_access_size = 4,
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 31/40] openpic: fix minor coding style issues
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (29 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 30/40] MSI-X: Fix endianness Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 32/40] openpic: Accelerate pending irq search Alexander Graf
                   ` (9 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

This patch removes all remaining occurences of spaces before function
parameter indicating parenthesis.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 4bea1e7..25d5cd7 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -140,17 +140,17 @@
 #define BF_WIDTH(_bits_) \
 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
 
-static inline void set_bit (uint32_t *field, int bit)
+static inline void set_bit(uint32_t *field, int bit)
 {
     field[bit >> 5] |= 1 << (bit & 0x1F);
 }
 
-static inline void reset_bit (uint32_t *field, int bit)
+static inline void reset_bit(uint32_t *field, int bit)
 {
     field[bit >> 5] &= ~(1 << (bit & 0x1F));
 }
 
-static inline int test_bit (uint32_t *field, int bit)
+static inline int test_bit(uint32_t *field, int bit)
 {
     return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
 }
@@ -249,17 +249,17 @@ typedef struct OpenPICState {
 
 static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
 
-static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
+static inline void IRQ_setbit(IRQ_queue_t *q, int n_IRQ)
 {
     set_bit(q->queue, n_IRQ);
 }
 
-static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
+static inline void IRQ_resetbit(IRQ_queue_t *q, int n_IRQ)
 {
     reset_bit(q->queue, n_IRQ);
 }
 
-static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
+static inline int IRQ_testbit(IRQ_queue_t *q, int n_IRQ)
 {
     return test_bit(q->queue, n_IRQ);
 }
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 32/40] openpic: Accelerate pending irq search
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (30 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 31/40] openpic: fix minor coding style issues Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 33/40] PPC: E500: PCI: Make first slot qdev settable Alexander Graf
                   ` (8 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

When we're done with one interrupt, we need to search for the next pending
interrupt in the queue. This search has grown quite big now that we have
more than 256 possible irq lines.

So let's memorize how many interrupts we have pending in our bitmaps, so
that we can always bail out in the usual case - the one where we're all done.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/openpic.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/hw/openpic.c b/hw/openpic.c
index 25d5cd7..3cbcea8 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -169,6 +169,7 @@ typedef struct IRQ_queue_t {
     uint32_t queue[BF_WIDTH(MAX_IRQ)];
     int next;
     int priority;
+    int pending;    /* nr of pending bits in queue */
 } IRQ_queue_t;
 
 typedef struct IRQ_src_t {
@@ -251,11 +252,13 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
 
 static inline void IRQ_setbit(IRQ_queue_t *q, int n_IRQ)
 {
+    q->pending++;
     set_bit(q->queue, n_IRQ);
 }
 
 static inline void IRQ_resetbit(IRQ_queue_t *q, int n_IRQ)
 {
+    q->pending--;
     reset_bit(q->queue, n_IRQ);
 }
 
@@ -271,6 +274,12 @@ static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
 
     next = -1;
     priority = -1;
+
+    if (!q->pending) {
+        /* IRQ bitmap is empty */
+        goto out;
+    }
+
     for (i = 0; i < opp->max_irq; i++) {
         if (IRQ_testbit(q, i)) {
             DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
@@ -281,6 +290,8 @@ static void IRQ_check(OpenPICState *opp, IRQ_queue_t *q)
             }
         }
     }
+
+out:
     q->next = next;
     q->priority = priority;
 }
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 33/40] PPC: E500: PCI: Make first slot qdev settable
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (31 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 32/40] openpic: Accelerate pending irq search Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 34/40] PPC: E500: PCI: Make IRQ calculation more generic Alexander Graf
                   ` (7 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

Today the first slot id in our e500 pci implementation is hardcoded to
0x11. Keep it there as default, but allow users to change the default to
a different id.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_pci.c |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index e534341..4cd4edc 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -87,6 +87,7 @@ struct PPCE500PCIState {
     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
     uint32_t gasket_time;
     qemu_irq irq[4];
+    uint32_t first_slot;
     /* mmio maps */
     MemoryRegion container;
     MemoryRegion iomem;
@@ -361,7 +362,7 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
 
     b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
                          mpc85xx_pci_map_irq, s->irq, address_space_mem,
-                         &s->pio, PCI_DEVFN(0x11, 0), 4);
+                         &s->pio, PCI_DEVFN(s->first_slot, 0), 4);
     h->bus = b;
 
     pci_create_simple(b, 0, "e500-host-bridge");
@@ -401,12 +402,18 @@ static const TypeInfo e500_host_bridge_info = {
     .class_init    = e500_host_bridge_class_init,
 };
 
+static Property pcihost_properties[] = {
+    DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 
     k->init = e500_pcihost_initfn;
+    dc->props = pcihost_properties;
     dc->vmsd = &vmstate_ppce500_pci;
 }
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 34/40] PPC: E500: PCI: Make IRQ calculation more generic
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (32 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 33/40] PPC: E500: PCI: Make first slot qdev settable Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 35/40] PPC: E500: Generate dt pci irq map dynamically Alexander Graf
                   ` (6 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The IRQ line calculation is more or less hardcoded today. Instead, let's
write it as an algorithmic function that theoretically allows an arbitrary
number of PCI slots.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppce500_pci.c |   13 +++----------
 1 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 4cd4edc..561a776 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -253,17 +253,10 @@ static const MemoryRegionOps e500_pci_reg_ops = {
 
 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 {
-    int devno = pci_dev->devfn >> 3, ret = 0;
+    int devno = pci_dev->devfn >> 3;
+    int ret;
 
-    switch (devno) {
-        /* Two PCI slot */
-        case 0x11:
-        case 0x12:
-            ret = (irq_num + devno - 0x10) % 4;
-            break;
-        default:
-            printf("Error:%s:unknown dev number\n", __func__);
-    }
+    ret = (irq_num + devno) % 4;
 
     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
            pci_dev->devfn, irq_num, ret, devno);
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 35/40] PPC: E500: Generate dt pci irq map dynamically
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (33 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 34/40] PPC: E500: PCI: Make IRQ calculation more generic Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 36/40] PPC: E500: Move PCI slot information into params Alexander Graf
                   ` (5 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

Today we're hardcoding the PCI interrupt map in the e500 machine file.
Instead, let's write it dynamically so that different machine types
can have different slot properties.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/e500.c |   51 +++++++++++++++++++++++++++++++--------------------
 1 files changed, 31 insertions(+), 20 deletions(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 1034f93..ebb6d96 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -66,25 +66,33 @@ struct boot_info
     uint32_t entry;
 };
 
-static void pci_map_create(void *fdt, uint32_t *pci_map, uint32_t mpic)
+static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
+                                int nr_slots, int *len)
 {
-    int i;
-    const uint32_t tmp[] = {
-                             /* IDSEL 0x11 J17 Slot 1 */
-                             0x8800, 0x0, 0x0, 0x1, mpic, 0x2, 0x1,
-                             0x8800, 0x0, 0x0, 0x2, mpic, 0x3, 0x1,
-                             0x8800, 0x0, 0x0, 0x3, mpic, 0x4, 0x1,
-                             0x8800, 0x0, 0x0, 0x4, mpic, 0x1, 0x1,
-
-                             /* IDSEL 0x12 J16 Slot 2 */
-                             0x9000, 0x0, 0x0, 0x1, mpic, 0x3, 0x1,
-                             0x9000, 0x0, 0x0, 0x2, mpic, 0x4, 0x1,
-                             0x9000, 0x0, 0x0, 0x3, mpic, 0x2, 0x1,
-                             0x9000, 0x0, 0x0, 0x4, mpic, 0x1, 0x1,
-                           };
-    for (i = 0; i < (7 * 8); i++) {
-        pci_map[i] = cpu_to_be32(tmp[i]);
+    int i = 0;
+    int slot;
+    int pci_irq;
+    int last_slot = first_slot + nr_slots;
+    uint32_t *pci_map;
+
+    *len = nr_slots * 4 * 7 * sizeof(uint32_t);
+    pci_map = g_malloc(*len);
+
+    for (slot = first_slot; slot < last_slot; slot++) {
+        for (pci_irq = 0; pci_irq < 4; pci_irq++) {
+            pci_map[i++] = cpu_to_be32(slot << 11);
+            pci_map[i++] = cpu_to_be32(0x0);
+            pci_map[i++] = cpu_to_be32(0x0);
+            pci_map[i++] = cpu_to_be32(pci_irq + 1);
+            pci_map[i++] = cpu_to_be32(mpic);
+            pci_map[i++] = cpu_to_be32(((pci_irq + slot) % 4) + 1);
+            pci_map[i++] = cpu_to_be32(0x1);
+        }
     }
+
+    assert((i * sizeof(uint32_t)) == *len);
+
+    return pci_map;
 }
 
 static void dt_serial_create(void *fdt, unsigned long long offset,
@@ -132,7 +140,8 @@ static int ppce500_load_device_tree(CPUPPCState *env,
     char gutil[128];
     char pci[128];
     char msi[128];
-    uint32_t pci_map[7 * 8];
+    uint32_t *pci_map = NULL;
+    int len;
     uint32_t pci_ranges[14] =
         {
             0x2000000, 0x0, 0xc0000000,
@@ -329,8 +338,9 @@ static int ppce500_load_device_tree(CPUPPCState *env,
     qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
                                0x0, 0x7);
-    pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic));
-    qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map));
+    pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
+                             0x11, 2, &len);
+    qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
     qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
@@ -364,6 +374,7 @@ done:
     ret = fdt_size;
 
 out:
+    g_free(pci_map);
 
     return ret;
 }
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 36/40] PPC: E500: Move PCI slot information into params
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (34 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 35/40] PPC: E500: Generate dt pci irq map dynamically Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 37/40] PPC: E500plat: Make a lot of PCI slots available Alexander Graf
                   ` (4 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

We have a params struct that allows us to expose differences between
e500 machine models. Include PCI slot information there, so we can have
different machines with different PCI slot topology.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/e500.c      |    4 +++-
 hw/ppc/e500.h      |    2 ++
 hw/ppc/e500plat.c  |    2 ++
 hw/ppc/mpc8544ds.c |    2 ++
 4 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index ebb6d96..564f654 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -339,7 +339,8 @@ static int ppce500_load_device_tree(CPUPPCState *env,
     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
                                0x0, 0x7);
     pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
-                             0x11, 2, &len);
+                             params->pci_first_slot, params->pci_nr_slots,
+                             &len);
     qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
@@ -569,6 +570,7 @@ void ppce500_init(PPCE500Params *params)
 
     /* PCI */
     dev = qdev_create(NULL, "e500-pcihost");
+    qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
     qdev_init_nofail(dev);
     s = SYS_BUS_DEVICE(dev);
     sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 7ae87f4..f5ff273 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -9,6 +9,8 @@ typedef struct PPCE500Params {
     const char *kernel_cmdline;
     const char *initrd_filename;
     const char *cpu_model;
+    int pci_first_slot;
+    int pci_nr_slots;
 
     /* e500-specific params */
 
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 4cfb940..9365213 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -40,6 +40,8 @@ static void e500plat_init(QEMUMachineInitArgs *args)
         .kernel_cmdline = kernel_cmdline,
         .initrd_filename = initrd_filename,
         .cpu_model = cpu_model,
+        .pci_first_slot = 0x11,
+        .pci_nr_slots = 2,
         .fixup_devtree = e500plat_fixup_devtree,
     };
 
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index e651661..7e1761d 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -40,6 +40,8 @@ static void mpc8544ds_init(QEMUMachineInitArgs *args)
         .kernel_cmdline = kernel_cmdline,
         .initrd_filename = initrd_filename,
         .cpu_model = cpu_model,
+        .pci_first_slot = 0x11,
+        .pci_nr_slots = 2,
         .fixup_devtree = mpc8544ds_fixup_devtree,
     };
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 37/40] PPC: E500plat: Make a lot of PCI slots available
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (35 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 36/40] PPC: E500: Move PCI slot information into params Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 38/40] PPC: e500: pci: Export slot2irq calculation Alexander Graf
                   ` (3 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

The ppce500 machine doesn't have to stick to hardware limitations,
as it's defined as being fully device tree based.

Thus we can change the initial PCI slot ID to 0x1 which gives us a
whopping 31 PCI devices we can support with this machine now!

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/e500plat.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 9365213..2992bd9 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -14,6 +14,7 @@
 #include "e500.h"
 #include "../boards.h"
 #include "device_tree.h"
+#include "hw/pci.h"
 
 static void e500plat_fixup_devtree(PPCE500Params *params, void *fdt)
 {
@@ -40,8 +41,8 @@ static void e500plat_init(QEMUMachineInitArgs *args)
         .kernel_cmdline = kernel_cmdline,
         .initrd_filename = initrd_filename,
         .cpu_model = cpu_model,
-        .pci_first_slot = 0x11,
-        .pci_nr_slots = 2,
+        .pci_first_slot = 0x1,
+        .pci_nr_slots = PCI_SLOT_MAX - 1,
         .fixup_devtree = e500plat_fixup_devtree,
     };
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 38/40] PPC: e500: pci: Export slot2irq calculation
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (36 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 37/40] PPC: E500plat: Make a lot of PCI slots available Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 39/40] target-ppc: Don't use hwaddr to represent hardware state Alexander Graf
                   ` (2 subsequent siblings)
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel

We need the calculation method to get from a PCI slot ID to its respective
interrupt line twice. Once in the internal map function and once when
assembling the device tree.

So let's extract the calculation to a separate function that can be called
by both users.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/ppc/e500.c    |    5 ++++-
 hw/ppce500_pci.c |    3 ++-
 hw/ppce500_pci.h |    9 +++++++++
 3 files changed, 15 insertions(+), 2 deletions(-)
 create mode 100644 hw/ppce500_pci.h

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 564f654..af6b671 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -34,6 +34,7 @@
 #include "hw/sysbus.h"
 #include "exec-memory.h"
 #include "host-utils.h"
+#include "hw/ppce500_pci.h"
 
 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
 #define UIMAGE_LOAD_BASE           0
@@ -72,6 +73,7 @@ static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
     int i = 0;
     int slot;
     int pci_irq;
+    int host_irq;
     int last_slot = first_slot + nr_slots;
     uint32_t *pci_map;
 
@@ -85,7 +87,8 @@ static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
             pci_map[i++] = cpu_to_be32(0x0);
             pci_map[i++] = cpu_to_be32(pci_irq + 1);
             pci_map[i++] = cpu_to_be32(mpic);
-            pci_map[i++] = cpu_to_be32(((pci_irq + slot) % 4) + 1);
+            host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
+            pci_map[i++] = cpu_to_be32(host_irq + 1);
             pci_map[i++] = cpu_to_be32(0x1);
         }
     }
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 561a776..09e3507 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -19,6 +19,7 @@
 #include "pci.h"
 #include "pci_host.h"
 #include "bswap.h"
+#include "ppce500_pci.h"
 
 #ifdef DEBUG_PCI
 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
@@ -256,7 +257,7 @@ static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
     int devno = pci_dev->devfn >> 3;
     int ret;
 
-    ret = (irq_num + devno) % 4;
+    ret = ppce500_pci_map_irq_slot(devno, irq_num);
 
     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
            pci_dev->devfn, irq_num, ret, devno);
diff --git a/hw/ppce500_pci.h b/hw/ppce500_pci.h
new file mode 100644
index 0000000..61f773e
--- /dev/null
+++ b/hw/ppce500_pci.h
@@ -0,0 +1,9 @@
+#ifndef PPCE500_PCI_H
+#define PPCE500_PCI_H
+
+static inline int ppce500_pci_map_irq_slot(int devno, int irq_num)
+{
+    return (devno + irq_num) % 4;
+}
+
+#endif
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 39/40] target-ppc: Don't use hwaddr to represent hardware state
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (37 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 38/40] PPC: e500: pci: Export slot2irq calculation Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 40/40] pseries: Increase default NVRAM size Alexander Graf
  2012-12-15 10:09 ` [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Blue Swirl
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: David Gibson <david@gibson.dropbear.id.au>

The hwaddr type is somewhat vaguely defined as being able to contain bus
addresses on the widest possible bus in the system.  For that reason it's
discouraged for representing specific pieces of persistent hardware state,
which should instead use an explicit width type that matches the bits
available in real hardware.  In particular, because of the possibility that
the size of hwaddr might change if different buses are added to the target
in future, it's not suitable for use in vm state descriptions for savevm
and migration.

This patch purges such unwise uses of hwaddr from the ppc target code,
which turns out to be just one.  The ppcemb_tlb_t struct, used on a number
of embedded ppc models to represent a TLB entry contains a hwaddr for the
real address field.  This patch changes it to be a fixed uint64_t which is
suitable enough for all machine types which use this structure.

Other uses of hwaddr in CPUPPCState turn out not to be problematic:
htab_base and htab_mask are just used for the convenience of the TCG code;
the underlying machine state is the SDR1 register, which is stored with
a suitable type already.  Likewise the mpic_cpu_base field is only used
internally and does not represent fundamental hardware state which needs to
be saved.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/cpu.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 5f1dc8b..742d4f8 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -355,7 +355,7 @@ struct ppc6xx_tlb_t {

 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 struct ppcemb_tlb_t {
-    hwaddr RPN;
+    uint64_t RPN;
     target_ulong EPN;
     target_ulong PID;
     target_ulong size;
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* [Qemu-devel] [PATCH 40/40] pseries: Increase default NVRAM size
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (38 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 39/40] target-ppc: Don't use hwaddr to represent hardware state Alexander Graf
@ 2012-12-14 12:13 ` Alexander Graf
  2012-12-15 10:09 ` [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Blue Swirl
  40 siblings, 0 replies; 47+ messages in thread
From: Alexander Graf @ 2012-12-14 12:13 UTC (permalink / raw)
  To: qemu-ppc@nongnu.org List; +Cc: qemu-devel qemu-devel, David Gibson

From: David Gibson <david@gibson.dropbear.id.au>

If no image file for NVRAM is specified, the pseries machine currently
creates a 16K non-persistent NVRAM by default.  This basically works, but
is not large enough for current firmware and guest kernels to create all
the NVRAM partitions they would like to.  Increasing the default size to
64K addresses this and stops the guest generating error messages.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
---
 hw/spapr_nvram.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/hw/spapr_nvram.c b/hw/spapr_nvram.c
index 641de48..512bb8d 100644
--- a/hw/spapr_nvram.c
+++ b/hw/spapr_nvram.c
@@ -37,7 +37,7 @@ typedef struct sPAPRNVRAM {
 } sPAPRNVRAM;
 
 #define MIN_NVRAM_SIZE 8192
-#define DEFAULT_NVRAM_SIZE 16384
+#define DEFAULT_NVRAM_SIZE 65536
 #define MAX_NVRAM_SIZE (UINT16_MAX * 16)
 
 static void rtas_nvram_fetch(sPAPREnvironment *spapr,
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 47+ messages in thread

* Re: [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14
  2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
                   ` (39 preceding siblings ...)
  2012-12-14 12:13 ` [Qemu-devel] [PATCH 40/40] pseries: Increase default NVRAM size Alexander Graf
@ 2012-12-15 10:09 ` Blue Swirl
  40 siblings, 0 replies; 47+ messages in thread
From: Blue Swirl @ 2012-12-15 10:09 UTC (permalink / raw)
  To: Alexander Graf
  Cc: qemu-ppc@nongnu.org List, qemu-devel qemu-devel, Aurelien Jarno

On Fri, Dec 14, 2012 at 12:13 PM, Alexander Graf <agraf@suse.de> wrote:
> Hi Blue / Aurelien,
>
> This is my current patch queue for ppc.  Please pull.

Thanks, pulled.

>
> Alex
>
>
> The following changes since commit 1c97e303d4ea80a2691334b0febe87a50660f99d:
>   Anthony Liguori (1):
>         Merge remote-tracking branch 'afaerber/qom-cpu' into staging
>
> are available in the git repository at:
>
>   git://repo.or.cz/qemu/agraf.git ppc-for-upstream
>
> Alexander Graf (27):
>       openpic: Remove unused code
>       mpic: Unify numbering scheme
>       openpic: update to proper memory api
>       openpic: combine mpic and openpic src handlers
>       openpic: Convert subregions to memory api
>       openpic: combine mpic and openpic irq raise functions
>       openpic: merge mpic and openpic timer handling
>       openpic: combine openpic and mpic reset functions
>       openpic: unify memory api subregions
>       openpic: remove unused type variable
>       openpic: convert simple reg operations to builtin bitops
>       openpic: rename openpic_t to OpenPICState
>       openpic: remove irq_out
>       openpic: convert to qdev
>       openpic: make brr1 model specific
>       openpic: add Shared MSI support
>       PPC: e500: Add MSI support
>       PPC: e500: Declare pci bridge as bridge
>       MSI-X: Fix endianness
>       openpic: fix minor coding style issues
>       openpic: Accelerate pending irq search
>       PPC: E500: PCI: Make first slot qdev settable
>       PPC: E500: PCI: Make IRQ calculation more generic
>       PPC: E500: Generate dt pci irq map dynamically
>       PPC: E500: Move PCI slot information into params
>       PPC: E500plat: Make a lot of PCI slots available
>       PPC: e500: pci: Export slot2irq calculation
>
> Ben Herrenschmidt (2):
>       pseries: Use #define for XICS base irq number
>       pseries: Allow RTAS tokens without a qemu handler
>
> Bharat Bhushan (2):
>       e500: Adding CCSR memory region
>       Adding BAR0 for e500 PCI controller
>
> David Gibson (8):
>       pseries: Fix incorrect initialization of interrupt controller
>       pseries: Add tracepoints to the XICS interrupt controller
>       pseries: Split xics irq configuration from state information
>       pseries: Implement PAPR NVRAM
>       pseries: Update SLOF for NVRAM support
>       pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs
>       target-ppc: Don't use hwaddr to represent hardware state
>       pseries: Increase default NVRAM size
>
> Michael Ellerman (1):
>       pseries: Return the token when we register an RTAS call
>
>  hw/msix.c            |    6 +-
>  hw/openpic.c         | 1397 ++++++++++++++++++--------------------------------
>  hw/openpic.h         |    7 +-
>  hw/ppc/Makefile.objs |    2 +-
>  hw/ppc/e500-ccsr.h   |   17 +
>  hw/ppc/e500.c        |  205 ++++++--
>  hw/ppc/e500.h        |    2 +
>  hw/ppc/e500plat.c    |    3 +
>  hw/ppc/mpc8544ds.c   |    2 +
>  hw/ppc_newworld.c    |   25 +-
>  hw/ppce500_pci.c     |   58 ++-
>  hw/ppce500_pci.h     |    9 +
>  hw/spapr.c           |   35 ++-
>  hw/spapr.h           |    4 +-
>  hw/spapr_iommu.c     |    6 +
>  hw/spapr_nvram.c     |  196 +++++++
>  hw/spapr_rtas.c      |    6 +-
>  hw/xics.c            |   47 ++-
>  hw/xics.h            |    1 +
>  pc-bios/README       |    2 +-
>  pc-bios/slof.bin     |  Bin 878640 -> 880832 bytes
>  qemu-config.c        |    4 +
>  roms/SLOF            |    2 +-
>  target-ppc/cpu.h     |    2 +-
>  trace-events         |   13 +
>  25 files changed, 1043 insertions(+), 1008 deletions(-)
>  create mode 100644 hw/ppc/e500-ccsr.h
>  create mode 100644 hw/ppce500_pci.h
>  create mode 100644 hw/spapr_nvram.c
>

^ permalink raw reply	[flat|nested] 47+ messages in thread

end of thread, other threads:[~2012-12-15 10:09 UTC | newest]

Thread overview: 47+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-12-14 12:13 [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 01/40] pseries: Fix incorrect initialization of interrupt controller Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 02/40] pseries: Use #define for XICS base irq number Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 03/40] pseries: Return the token when we register an RTAS call Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 04/40] pseries: Allow RTAS tokens without a qemu handler Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 05/40] pseries: Add tracepoints to the XICS interrupt controller Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 06/40] pseries: Split xics irq configuration from state information Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 07/40] pseries: Implement PAPR NVRAM Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 08/40] pseries: Update SLOF for NVRAM support Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 09/40] e500: Adding CCSR memory region Alexander Graf
2012-12-14 13:47   ` Andreas Färber
2012-12-14 12:13 ` [Qemu-devel] [PATCH 10/40] Adding BAR0 for e500 PCI controller Alexander Graf
2012-12-14 13:49   ` Andreas Färber
2012-12-14 12:13 ` [Qemu-devel] [PATCH 11/40] pseries: Don't allow TCE (iommu) tables to be registered with duplicate LIOBNs Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 12/40] openpic: Remove unused code Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 13/40] mpic: Unify numbering scheme Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 14/40] openpic: update to proper memory api Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 15/40] openpic: combine mpic and openpic src handlers Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 16/40] openpic: Convert subregions to memory api Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 17/40] openpic: combine mpic and openpic irq raise functions Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 18/40] openpic: merge mpic and openpic timer handling Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 19/40] openpic: combine openpic and mpic reset functions Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 20/40] openpic: unify memory api subregions Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 21/40] openpic: remove unused type variable Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 22/40] openpic: convert simple reg operations to builtin bitops Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 23/40] openpic: rename openpic_t to OpenPICState Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 24/40] openpic: remove irq_out Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 25/40] openpic: convert to qdev Alexander Graf
2012-12-14 20:32   ` Blue Swirl
2012-12-14 20:42     ` Alexander Graf
2012-12-14 20:50       ` Blue Swirl
2012-12-14 12:13 ` [Qemu-devel] [PATCH 26/40] openpic: make brr1 model specific Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 27/40] openpic: add Shared MSI support Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 28/40] PPC: e500: Add " Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 29/40] PPC: e500: Declare pci bridge as bridge Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 30/40] MSI-X: Fix endianness Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 31/40] openpic: fix minor coding style issues Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 32/40] openpic: Accelerate pending irq search Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 33/40] PPC: E500: PCI: Make first slot qdev settable Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 34/40] PPC: E500: PCI: Make IRQ calculation more generic Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 35/40] PPC: E500: Generate dt pci irq map dynamically Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 36/40] PPC: E500: Move PCI slot information into params Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 37/40] PPC: E500plat: Make a lot of PCI slots available Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 38/40] PPC: e500: pci: Export slot2irq calculation Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 39/40] target-ppc: Don't use hwaddr to represent hardware state Alexander Graf
2012-12-14 12:13 ` [Qemu-devel] [PATCH 40/40] pseries: Increase default NVRAM size Alexander Graf
2012-12-15 10:09 ` [Qemu-devel] [PULL 00/40] ppc patch queue 2012-12-14 Blue Swirl

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