* [Qemu-devel] [FYI qom-cpu v2 1/5] target-alpha: Let cpu_alpha_init() return AlphaCPU
2012-12-09 1:40 [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Andreas Färber
@ 2012-12-09 1:40 ` Andreas Färber
2012-12-09 1:40 ` [Qemu-devel] [FYI qom-cpu v2 2/5] alpha: Pass AlphaCPU array to Typhoon Andreas Färber
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Andreas Färber @ 2012-12-09 1:40 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, rth
Replace cpu_init() macro with inline function for backwards
compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/cpu.h | 13 +++++++++++--
target-alpha/translate.c | 4 ++--
2 Dateien geändert, 13 Zeilen hinzugefügt(+), 4 Zeilen entfernt(-)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 34221fb..853ea8e 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -297,7 +297,6 @@ struct CPUAlphaState {
int implver;
};
-#define cpu_init cpu_alpha_init
#define cpu_exec cpu_alpha_exec
#define cpu_gen_code cpu_alpha_gen_code
#define cpu_signal_handler cpu_alpha_signal_handler
@@ -434,7 +433,17 @@ enum {
IR_ZERO = 31,
};
-CPUAlphaState * cpu_alpha_init (const char *cpu_model);
+AlphaCPU *cpu_alpha_init(const char *cpu_model);
+
+static inline CPUAlphaState *cpu_init(const char *cpu_model)
+{
+ AlphaCPU *cpu = cpu_alpha_init(cpu_model);
+ if (cpu == NULL) {
+ return NULL;
+ }
+ return &cpu->env;
+}
+
int cpu_alpha_exec(CPUAlphaState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 4045f78..638a4a2 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3517,7 +3517,7 @@ static const struct cpu_def_t cpu_defs[] = {
| AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }
};
-CPUAlphaState * cpu_alpha_init (const char *cpu_model)
+AlphaCPU *cpu_alpha_init(const char *cpu_model)
{
AlphaCPU *cpu;
CPUAlphaState *env;
@@ -3546,7 +3546,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
env->cpu_model_str = cpu_model;
qemu_init_vcpu(env);
- return env;
+ return cpu;
}
void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos)
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [FYI qom-cpu v2 2/5] alpha: Pass AlphaCPU array to Typhoon
2012-12-09 1:40 [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Andreas Färber
2012-12-09 1:40 ` [Qemu-devel] [FYI qom-cpu v2 1/5] target-alpha: Let cpu_alpha_init() return AlphaCPU Andreas Färber
@ 2012-12-09 1:40 ` Andreas Färber
2012-12-09 1:40 ` [Qemu-devel] [FYI qom-cpu v2 3/5] target-alpha: Avoid leaking the alarm timer over reset Andreas Färber
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Andreas Färber @ 2012-12-09 1:40 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, rth
Also store it in TyphoonCchip.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Richard Henderson <rth@twiddle.net>
---
hw/alpha_dp264.c | 18 +++++++++---------
hw/alpha_sys.h | 2 +-
hw/alpha_typhoon.c | 29 ++++++++++++++++-------------
3 Dateien geändert, 26 Zeilen hinzugefügt(+), 23 Zeilen entfernt(-)
diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
index 76d8ae8..af24d1e 100644
--- a/hw/alpha_dp264.c
+++ b/hw/alpha_dp264.c
@@ -50,7 +50,7 @@ static void clipper_init(QEMUMachineInitArgs *args)
const char *kernel_filename = args->kernel_filename;
const char *kernel_cmdline = args->kernel_cmdline;
const char *initrd_filename = args->initrd_filename;
- CPUAlphaState *cpus[4];
+ AlphaCPU *cpus[4];
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq rtc_irq;
@@ -62,12 +62,12 @@ static void clipper_init(QEMUMachineInitArgs *args)
/* Create up to 4 cpus. */
memset(cpus, 0, sizeof(cpus));
for (i = 0; i < smp_cpus; ++i) {
- cpus[i] = cpu_init(cpu_model ? cpu_model : "ev67");
+ cpus[i] = cpu_alpha_init(cpu_model ? cpu_model : "ev67");
}
- cpus[0]->trap_arg0 = ram_size;
- cpus[0]->trap_arg1 = 0;
- cpus[0]->trap_arg2 = smp_cpus;
+ cpus[0]->env.trap_arg0 = ram_size;
+ cpus[0]->env.trap_arg1 = 0;
+ cpus[0]->env.trap_arg2 = smp_cpus;
/* Init the chipset. */
pci_bus = typhoon_init(ram_size, &isa_bus, &rtc_irq, cpus,
@@ -119,9 +119,9 @@ static void clipper_init(QEMUMachineInitArgs *args)
/* Start all cpus at the PALcode RESET entry point. */
for (i = 0; i < smp_cpus; ++i) {
- cpus[i]->pal_mode = 1;
- cpus[i]->pc = palcode_entry;
- cpus[i]->palbr = palcode_entry;
+ cpus[i]->env.pal_mode = 1;
+ cpus[i]->env.pc = palcode_entry;
+ cpus[i]->env.palbr = palcode_entry;
}
/* Load a kernel. */
@@ -136,7 +136,7 @@ static void clipper_init(QEMUMachineInitArgs *args)
exit(1);
}
- cpus[0]->trap_arg1 = kernel_entry;
+ cpus[0]->env.trap_arg1 = kernel_entry;
param_offset = kernel_low - 0x6000;
diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h
index 7604d09..69929ea 100644
--- a/hw/alpha_sys.h
+++ b/hw/alpha_sys.h
@@ -11,7 +11,7 @@
#include "irq.h"
-PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUAlphaState *[4],
+PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, AlphaCPU *[4],
pci_map_irq_fn);
/* alpha_pci.c. */
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index 9b16d96..4cc810f 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -23,7 +23,7 @@ typedef struct TyphoonCchip {
uint64_t drir;
uint64_t dim[4];
uint32_t iic[4];
- CPUAlphaState *cpu[4];
+ AlphaCPU *cpu[4];
} TyphoonCchip;
typedef struct TyphoonWindow {
@@ -58,10 +58,11 @@ typedef struct TyphoonState {
} TyphoonState;
/* Called when one of DRIR or DIM changes. */
-static void cpu_irq_change(CPUAlphaState *env, uint64_t req)
+static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)
{
/* If there are any non-masked interrupts, tell the cpu. */
- if (env) {
+ if (cpu != NULL) {
+ CPUAlphaState *env = &cpu->env;
if (req) {
cpu_interrupt(env, CPU_INTERRUPT_HARD);
} else {
@@ -353,8 +354,9 @@ static void cchip_write(void *opaque, hwaddr addr,
if ((newval ^ oldval) & 0xff0) {
int i;
for (i = 0; i < 4; ++i) {
- CPUAlphaState *env = s->cchip.cpu[i];
- if (env) {
+ AlphaCPU *cpu = s->cchip.cpu[i];
+ if (cpu != NULL) {
+ CPUAlphaState *env = &cpu->env;
/* IPI can be either cleared or set by the write. */
if (newval & (1 << (i + 8))) {
cpu_interrupt(env, CPU_INTERRUPT_SMP);
@@ -661,8 +663,8 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level)
/* Deliver the interrupt to each CPU, considering each CPU's IIC. */
for (i = 0; i < 4; ++i) {
- CPUAlphaState *env = s->cchip.cpu[i];
- if (env) {
+ AlphaCPU *cpu = s->cchip.cpu[i];
+ if (cpu != NULL) {
uint32_t iic = s->cchip.iic[i];
/* ??? The verbage in Section 10.2.2.10 isn't 100% clear.
@@ -681,7 +683,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level)
/* Set the ITI bit for this cpu. */
s->cchip.misc |= 1 << (i + 4);
/* And signal the interrupt. */
- cpu_interrupt(env, CPU_INTERRUPT_TIMER);
+ cpu_interrupt(&cpu->env, CPU_INTERRUPT_TIMER);
}
}
}
@@ -694,12 +696,12 @@ static void typhoon_alarm_timer(void *opaque)
/* Set the ITI bit for this cpu. */
s->cchip.misc |= 1 << (cpu + 4);
- cpu_interrupt(s->cchip.cpu[cpu], CPU_INTERRUPT_TIMER);
+ cpu_interrupt(&s->cchip.cpu[cpu]->env, CPU_INTERRUPT_TIMER);
}
PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
qemu_irq *p_rtc_irq,
- CPUAlphaState *cpus[4], pci_map_irq_fn sys_map_irq)
+ AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq)
{
const uint64_t MB = 1024 * 1024;
const uint64_t GB = 1024 * MB;
@@ -719,9 +721,10 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
/* Remember the CPUs so that we can deliver interrupts to them. */
for (i = 0; i < 4; i++) {
- CPUAlphaState *env = cpus[i];
- s->cchip.cpu[i] = env;
- if (env) {
+ AlphaCPU *cpu = cpus[i];
+ s->cchip.cpu[i] = cpu;
+ if (cpu != NULL) {
+ CPUAlphaState *env = &cpu->env;
env->alarm_timer = qemu_new_timer_ns(rtc_clock,
typhoon_alarm_timer,
(void *)((uintptr_t)s + i));
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [FYI qom-cpu v2 3/5] target-alpha: Avoid leaking the alarm timer over reset
2012-12-09 1:40 [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Andreas Färber
2012-12-09 1:40 ` [Qemu-devel] [FYI qom-cpu v2 1/5] target-alpha: Let cpu_alpha_init() return AlphaCPU Andreas Färber
2012-12-09 1:40 ` [Qemu-devel] [FYI qom-cpu v2 2/5] alpha: Pass AlphaCPU array to Typhoon Andreas Färber
@ 2012-12-09 1:40 ` Andreas Färber
2012-12-09 1:40 ` [Qemu-devel] [PATCH qom-cpu v2 4/5] target-alpha: Turn CPU definitions into subclasses Andreas Färber
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Andreas Färber @ 2012-12-09 1:40 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, rth
Move the timer from CPUAlphaState to AlphaCPU to avoid the pointer being
zero'ed once we implement reset. Would cause a segfault in
sys_helper.c:helper_set_alarm().
This also simplifies timer initialization in Typhoon.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Richard Henderson <rth@twiddle.net>
---
hw/alpha_typhoon.c | 3 +--
target-alpha/cpu-qom.h | 3 +++
target-alpha/cpu.h | 1 -
target-alpha/sys_helper.c | 6 ++++--
4 Dateien geändert, 8 Zeilen hinzugefügt(+), 5 Zeilen entfernt(-)
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index 4cc810f..40b3a47 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -724,8 +724,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
AlphaCPU *cpu = cpus[i];
s->cchip.cpu[i] = cpu;
if (cpu != NULL) {
- CPUAlphaState *env = &cpu->env;
- env->alarm_timer = qemu_new_timer_ns(rtc_clock,
+ cpu->alarm_timer = qemu_new_timer_ns(rtc_clock,
typhoon_alarm_timer,
(void *)((uintptr_t)s + i));
}
diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h
index 6b4ca6d..98585d5 100644
--- a/target-alpha/cpu-qom.h
+++ b/target-alpha/cpu-qom.h
@@ -58,6 +58,9 @@ typedef struct AlphaCPU {
/*< public >*/
CPUAlphaState env;
+
+ /* This alarm doesn't exist in real hardware; we wish it did. */
+ struct QEMUTimer *alarm_timer;
} AlphaCPU;
static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 853ea8e..ff48c1a 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -277,7 +277,6 @@ struct CPUAlphaState {
#endif
/* This alarm doesn't exist in real hardware; we wish it did. */
- struct QEMUTimer *alarm_timer;
uint64_t alarm_expire;
#if TARGET_LONG_BITS > HOST_LONG_BITS
diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
index 40ca49c..d4f14ef 100644
--- a/target-alpha/sys_helper.c
+++ b/target-alpha/sys_helper.c
@@ -77,11 +77,13 @@ uint64_t helper_get_time(void)
void helper_set_alarm(CPUAlphaState *env, uint64_t expire)
{
+ AlphaCPU *cpu = alpha_env_get_cpu(env);
+
if (expire) {
env->alarm_expire = expire;
- qemu_mod_timer(env->alarm_timer, expire);
+ qemu_mod_timer(cpu->alarm_timer, expire);
} else {
- qemu_del_timer(env->alarm_timer);
+ qemu_del_timer(cpu->alarm_timer);
}
}
#endif /* CONFIG_USER_ONLY */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* [Qemu-devel] [PATCH qom-cpu v2 4/5] target-alpha: Turn CPU definitions into subclasses
2012-12-09 1:40 [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Andreas Färber
` (2 preceding siblings ...)
2012-12-09 1:40 ` [Qemu-devel] [FYI qom-cpu v2 3/5] target-alpha: Avoid leaking the alarm timer over reset Andreas Färber
@ 2012-12-09 1:40 ` Andreas Färber
2012-12-18 23:00 ` Andreas Färber
2012-12-09 1:40 ` [Qemu-devel] [PATCH qom-cpu v2 5/5] target-alpha: Add support for -cpu ? Andreas Färber
2012-12-10 17:18 ` [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Richard Henderson
5 siblings, 1 reply; 9+ messages in thread
From: Andreas Färber @ 2012-12-09 1:40 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, Eduardo Habkost, rth
Make TYPE_ALPHA_CPU abstract and add types <name>-alpha-cpu.
Use type inheritence, and turn "2*" models into aliases.
Move cpu_alpha_init() to cpu.c and split out CPU realization.
Default to creating type "ev67-alpha-cpu" as before.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Eduardo Habkost <ehabkost@redhat.com>
---
target-alpha/cpu.c | 178 +++++++++++++++++++++++++++++++++++++++++++++-
target-alpha/cpu.h | 2 +
target-alpha/translate.c | 58 +--------------
3 Dateien geändert, 180 Zeilen hinzugefügt(+), 58 Zeilen entfernt(-)
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 11a19eb..11df753 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -21,8 +21,175 @@
#include "cpu.h"
#include "qemu-common.h"
+#include "error.h"
+static void alpha_cpu_realize(Object *obj, Error **err)
+{
+#ifndef CONFIG_USER_ONLY
+ AlphaCPU *cpu = ALPHA_CPU(obj);
+
+ qemu_init_vcpu(&cpu->env);
+#endif
+}
+
+/* Models */
+
+#define TYPE(model) model "-" TYPE_ALPHA_CPU
+
+typedef struct AlphaCPUAlias {
+ const char *alias;
+ const char *typename;
+} AlphaCPUAlias;
+
+static const AlphaCPUAlias alpha_cpu_aliases[] = {
+ { "21064", TYPE("ev4") },
+ { "21164", TYPE("ev5") },
+ { "21164a", TYPE("ev56") },
+ { "21164pc", TYPE("pca56") },
+ { "21264", TYPE("ev6") },
+ { "21264a", TYPE("ev67") },
+};
+
+static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
+{
+ ObjectClass *oc = NULL;
+ char *typename;
+ int i;
+
+ if (cpu_model == NULL) {
+ return NULL;
+ }
+
+ oc = object_class_by_name(cpu_model);
+ if (oc != NULL) {
+ return oc;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) {
+ if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) {
+ oc = object_class_by_name(alpha_cpu_aliases[i].typename);
+ assert(oc != NULL);
+ return oc;
+ }
+ }
+
+ typename = g_strdup_printf("%s-" TYPE_ALPHA_CPU, cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
+ return oc;
+}
+
+AlphaCPU *cpu_alpha_init(const char *cpu_model)
+{
+ AlphaCPU *cpu;
+ CPUAlphaState *env;
+ ObjectClass *cpu_class;
+
+ cpu_class = alpha_cpu_class_by_name(cpu_model);
+ if (cpu_class == NULL) {
+ /* Default to ev67; no reason not to emulate insns by default. */
+ cpu_class = object_class_by_name(TYPE("ev67"));
+ }
+ cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class)));
+ env = &cpu->env;
+
+ env->cpu_model_str = cpu_model;
+
+ alpha_cpu_realize(OBJECT(cpu), NULL);
+ return cpu;
+}
+
+static void ev4_cpu_initfn(Object *obj)
+{
+ AlphaCPU *cpu = ALPHA_CPU(obj);
+ CPUAlphaState *env = &cpu->env;
+
+ env->implver = IMPLVER_2106x;
+}
+
+static const TypeInfo ev4_cpu_type_info = {
+ .name = TYPE("ev4"),
+ .parent = TYPE_ALPHA_CPU,
+ .instance_init = ev4_cpu_initfn,
+};
+
+static void ev5_cpu_initfn(Object *obj)
+{
+ AlphaCPU *cpu = ALPHA_CPU(obj);
+ CPUAlphaState *env = &cpu->env;
+
+ env->implver = IMPLVER_21164;
+}
+
+static const TypeInfo ev5_cpu_type_info = {
+ .name = TYPE("ev5"),
+ .parent = TYPE_ALPHA_CPU,
+ .instance_init = ev5_cpu_initfn,
+};
+
+static void ev56_cpu_initfn(Object *obj)
+{
+ AlphaCPU *cpu = ALPHA_CPU(obj);
+ CPUAlphaState *env = &cpu->env;
+
+ env->amask |= AMASK_BWX;
+}
+
+static const TypeInfo ev56_cpu_type_info = {
+ .name = TYPE("ev56"),
+ .parent = TYPE("ev5"),
+ .instance_init = ev56_cpu_initfn,
+};
+
+static void pca56_cpu_initfn(Object *obj)
+{
+ AlphaCPU *cpu = ALPHA_CPU(obj);
+ CPUAlphaState *env = &cpu->env;
+
+ env->amask |= AMASK_MVI;
+}
+
+static const TypeInfo pca56_cpu_type_info = {
+ .name = TYPE("pca56"),
+ .parent = TYPE("ev56"),
+ .instance_init = pca56_cpu_initfn,
+};
+
+static void ev6_cpu_initfn(Object *obj)
+{
+ AlphaCPU *cpu = ALPHA_CPU(obj);
+ CPUAlphaState *env = &cpu->env;
+
+ env->implver = IMPLVER_21264;
+ env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
+}
+
+static const TypeInfo ev6_cpu_type_info = {
+ .name = TYPE("ev6"),
+ .parent = TYPE_ALPHA_CPU,
+ .instance_init = ev6_cpu_initfn,
+};
+
+static void ev67_cpu_initfn(Object *obj)
+{
+ AlphaCPU *cpu = ALPHA_CPU(obj);
+ CPUAlphaState *env = &cpu->env;
+
+ env->amask |= AMASK_CIX | AMASK_PREFETCH;
+}
+
+static const TypeInfo ev67_cpu_type_info = {
+ .name = TYPE("ev67"),
+ .parent = TYPE("ev6"),
+ .instance_init = ev67_cpu_initfn,
+};
+
+static const TypeInfo ev68_cpu_type_info = {
+ .name = TYPE("ev68"),
+ .parent = TYPE("ev67"),
+};
+
static void alpha_cpu_initfn(Object *obj)
{
AlphaCPU *cpu = ALPHA_CPU(obj);
@@ -31,6 +198,8 @@ static void alpha_cpu_initfn(Object *obj)
cpu_exec_init(env);
tlb_flush(env, 1);
+ alpha_translate_init();
+
#if defined(CONFIG_USER_ONLY)
env->ps = PS_USER_MODE;
cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
@@ -46,13 +215,20 @@ static const TypeInfo alpha_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(AlphaCPU),
.instance_init = alpha_cpu_initfn,
- .abstract = false,
+ .abstract = true,
.class_size = sizeof(AlphaCPUClass),
};
static void alpha_cpu_register_types(void)
{
type_register_static(&alpha_cpu_type_info);
+ type_register_static(&ev4_cpu_type_info);
+ type_register_static(&ev5_cpu_type_info);
+ type_register_static(&ev56_cpu_type_info);
+ type_register_static(&pca56_cpu_type_info);
+ type_register_static(&ev6_cpu_type_info);
+ type_register_static(&ev67_cpu_type_info);
+ type_register_static(&ev68_cpu_type_info);
}
type_init(alpha_cpu_register_types)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index ff48c1a..a5eb449 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -432,6 +432,8 @@ enum {
IR_ZERO = 31,
};
+void alpha_translate_init(void);
+
AlphaCPU *cpu_alpha_init(const char *cpu_model);
static inline CPUAlphaState *cpu_init(const char *cpu_model)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 638a4a2..9df8356 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -90,7 +90,7 @@ static char cpu_reg_names[10*4+21*5 + 10*5+21*6];
#include "gen-icount.h"
-static void alpha_translate_init(void)
+void alpha_translate_init(void)
{
int i;
char *p;
@@ -3493,62 +3493,6 @@ void gen_intermediate_code_pc (CPUAlphaState *env, struct TranslationBlock *tb)
gen_intermediate_code_internal(env, tb, 1);
}
-struct cpu_def_t {
- const char *name;
- int implver, amask;
-};
-
-static const struct cpu_def_t cpu_defs[] = {
- { "ev4", IMPLVER_2106x, 0 },
- { "ev5", IMPLVER_21164, 0 },
- { "ev56", IMPLVER_21164, AMASK_BWX },
- { "pca56", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
- { "ev6", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
- { "ev67", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
- { "ev68", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
- { "21064", IMPLVER_2106x, 0 },
- { "21164", IMPLVER_21164, 0 },
- { "21164a", IMPLVER_21164, AMASK_BWX },
- { "21164pc", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
- { "21264", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
- { "21264a", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
- | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }
-};
-
-AlphaCPU *cpu_alpha_init(const char *cpu_model)
-{
- AlphaCPU *cpu;
- CPUAlphaState *env;
- int implver, amask, i, max;
-
- cpu = ALPHA_CPU(object_new(TYPE_ALPHA_CPU));
- env = &cpu->env;
-
- alpha_translate_init();
-
- /* Default to ev67; no reason not to emulate insns by default. */
- implver = IMPLVER_21264;
- amask = (AMASK_BWX | AMASK_FIX | AMASK_CIX | AMASK_MVI
- | AMASK_TRAP | AMASK_PREFETCH);
-
- max = ARRAY_SIZE(cpu_defs);
- for (i = 0; i < max; i++) {
- if (strcmp (cpu_model, cpu_defs[i].name) == 0) {
- implver = cpu_defs[i].implver;
- amask = cpu_defs[i].amask;
- break;
- }
- }
- env->implver = implver;
- env->amask = amask;
- env->cpu_model_str = cpu_model;
-
- qemu_init_vcpu(env);
- return cpu;
-}
-
void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos)
{
env->pc = gen_opc_pc[pc_pos];
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH qom-cpu v2 4/5] target-alpha: Turn CPU definitions into subclasses
2012-12-09 1:40 ` [Qemu-devel] [PATCH qom-cpu v2 4/5] target-alpha: Turn CPU definitions into subclasses Andreas Färber
@ 2012-12-18 23:00 ` Andreas Färber
0 siblings, 0 replies; 9+ messages in thread
From: Andreas Färber @ 2012-12-18 23:00 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Eduardo Habkost
Am 09.12.2012 02:40, schrieb Andreas Färber:
> Make TYPE_ALPHA_CPU abstract and add types <name>-alpha-cpu.
> Use type inheritence, and turn "2*" models into aliases.
>
> Move cpu_alpha_init() to cpu.c and split out CPU realization.
> Default to creating type "ev67-alpha-cpu" as before.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Cc: Eduardo Habkost <ehabkost@redhat.com>
> ---
> target-alpha/cpu.c | 178 +++++++++++++++++++++++++++++++++++++++++++++-
> target-alpha/cpu.h | 2 +
> target-alpha/translate.c | 58 +--------------
> 3 Dateien geändert, 180 Zeilen hinzugefügt(+), 58 Zeilen entfernt(-)
>
> diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
> index 11a19eb..11df753 100644
> --- a/target-alpha/cpu.c
> +++ b/target-alpha/cpu.c
> @@ -21,8 +21,175 @@
>
> #include "cpu.h"
> #include "qemu-common.h"
> +#include "error.h"
>
>
> +static void alpha_cpu_realize(Object *obj, Error **err)
Should've been errp by convention, fixed.
No functional change since unused.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH qom-cpu v2 5/5] target-alpha: Add support for -cpu ?
2012-12-09 1:40 [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Andreas Färber
` (3 preceding siblings ...)
2012-12-09 1:40 ` [Qemu-devel] [PATCH qom-cpu v2 4/5] target-alpha: Turn CPU definitions into subclasses Andreas Färber
@ 2012-12-09 1:40 ` Andreas Färber
2012-12-10 17:18 ` [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Richard Henderson
5 siblings, 0 replies; 9+ messages in thread
From: Andreas Färber @ 2012-12-09 1:40 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber, rth
Implement alphabetical listing of CPU subclasses.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-alpha/cpu.c | 41 +++++++++++++++++++++++++++++++++++++++++
target-alpha/cpu.h | 2 ++
2 Dateien geändert, 43 Zeilen hinzugefügt(+)
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 11df753..d065085 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -33,6 +33,47 @@ static void alpha_cpu_realize(Object *obj, Error **err)
#endif
}
+typedef struct AlphaCPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} AlphaCPUListState;
+
+/* Sort alphabetically by type name. */
+static gint alpha_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+ const char *name_a, *name_b;
+
+ name_a = object_class_get_name(class_a);
+ name_b = object_class_get_name(class_b);
+ return strcmp(name_a, name_b);
+}
+
+static void alpha_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ AlphaCPUListState *s = user_data;
+
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ object_class_get_name(oc));
+}
+
+void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ AlphaCPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_ALPHA_CPU, false);
+ list = g_slist_sort(list, alpha_cpu_list_compare);
+ (*cpu_fprintf)(f, "Available CPUs:\n");
+ g_slist_foreach(list, alpha_cpu_list_entry, &s);
+ g_slist_free(list);
+}
+
/* Models */
#define TYPE(model) model "-" TYPE_ALPHA_CPU
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index a5eb449..867ee32 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -296,6 +296,7 @@ struct CPUAlphaState {
int implver;
};
+#define cpu_list alpha_cpu_list
#define cpu_exec cpu_alpha_exec
#define cpu_gen_code cpu_alpha_gen_code
#define cpu_signal_handler cpu_alpha_signal_handler
@@ -445,6 +446,7 @@ static inline CPUAlphaState *cpu_init(const char *cpu_model)
return &cpu->env;
}
+void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_alpha_exec(CPUAlphaState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses
2012-12-09 1:40 [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Andreas Färber
` (4 preceding siblings ...)
2012-12-09 1:40 ` [Qemu-devel] [PATCH qom-cpu v2 5/5] target-alpha: Add support for -cpu ? Andreas Färber
@ 2012-12-10 17:18 ` Richard Henderson
2012-12-14 14:03 ` Andreas Färber
5 siblings, 1 reply; 9+ messages in thread
From: Richard Henderson @ 2012-12-10 17:18 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Eduardo Habkost
On 12/08/2012 05:40 PM, Andreas Färber wrote:
> Andreas Färber (5):
> target-alpha: Let cpu_alpha_init() return AlphaCPU
> alpha: Pass AlphaCPU array to Typhoon
> target-alpha: Avoid leaking the alarm timer over reset
> target-alpha: Turn CPU definitions into subclasses
> target-alpha: Add support for -cpu ?
Looks ok.
Acked-by: Richard Henderson <rth@twiddle.net>
r~
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses
2012-12-10 17:18 ` [Qemu-devel] [PATCH qom-cpu v2 0/5] target-alpha: CPU subclasses Richard Henderson
@ 2012-12-14 14:03 ` Andreas Färber
0 siblings, 0 replies; 9+ messages in thread
From: Andreas Färber @ 2012-12-14 14:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Eduardo Habkost
Am 10.12.2012 18:18, schrieb Richard Henderson:
> On 12/08/2012 05:40 PM, Andreas Färber wrote:
>> Andreas Färber (5):
>> target-alpha: Let cpu_alpha_init() return AlphaCPU
>> alpha: Pass AlphaCPU array to Typhoon
>> target-alpha: Avoid leaking the alarm timer over reset
>> target-alpha: Turn CPU definitions into subclasses
>> target-alpha: Add support for -cpu ?
>
> Looks ok.
>
> Acked-by: Richard Henderson <rth@twiddle.net>
Thanks, applied to qom-cpu queue:
https://github.com/afaerber/qemu-cpu/commits/qom-cpu
I'll follow up by unifying the struct used for -cpu ?.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 9+ messages in thread