From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([208.118.235.92]:34168)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <paolo.bonzini@gmail.com>) id 1Tv9li-0006Tt-1t
	for qemu-devel@nongnu.org; Tue, 15 Jan 2013 11:53:47 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <paolo.bonzini@gmail.com>) id 1Tv9lf-0006pP-FH
	for qemu-devel@nongnu.org; Tue, 15 Jan 2013 11:53:45 -0500
Received: from mail-qc0-f170.google.com ([209.85.216.170]:59765)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <paolo.bonzini@gmail.com>) id 1Tv9lf-0006pK-Bt
	for qemu-devel@nongnu.org; Tue, 15 Jan 2013 11:53:43 -0500
Received: by mail-qc0-f170.google.com with SMTP id d42so209586qca.1
	for <qemu-devel@nongnu.org>; Tue, 15 Jan 2013 08:53:42 -0800 (PST)
Sender: Paolo Bonzini <paolo.bonzini@gmail.com>
Message-ID: <50F58992.90005@redhat.com>
Date: Tue, 15 Jan 2013 17:53:38 +0100
From: Paolo Bonzini <pbonzini@redhat.com>
MIME-Version: 1.0
References: <1358207252-23852-1-git-send-email-lersek@redhat.com>
In-Reply-To: <1358207252-23852-1-git-send-email-lersek@redhat.com>
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH] PIIX3: reset the VM when the Reset Control
 Register's RCPU bit gets set
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Laszlo Ersek <lersek@redhat.com>
Cc: blauwirbel@gmail.com, akong@redhat.com, qemu-devel@nongnu.org

Il 15/01/2013 00:47, Laszlo Ersek ha scritto:
> @@ -442,12 +455,14 @@ static void piix3_reset(void *opaque)
>      pci_conf[0xae] = 0x00;
>  
>      d->pic_levels = 0;
> +    d->rcr = 0;
>  }
>  
>  static int piix3_post_load(void *opaque, int version_id)
>  {
>      PIIX3State *piix3 = opaque;
>      piix3_update_irq_levels(piix3);
> +    piix3->rcr &= 2; /* keep System Reset type only */
>      return 0;
>  }
>  
> @@ -464,7 +479,7 @@ static void piix3_pre_save(void *opaque)
>  
>  static const VMStateDescription vmstate_piix3 = {
>      .name = "PIIX3",
> -    .version_id = 3,
> +    .version_id = 4,
>      .minimum_version_id = 2,
>      .minimum_version_id_old = 2,
>      .post_load = piix3_post_load,
> @@ -473,15 +488,46 @@ static const VMStateDescription vmstate_piix3 = {
>          VMSTATE_PCI_DEVICE(dev, PIIX3State),
>          VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
>                                PIIX_NUM_PIRQS, 3),
> +        VMSTATE_UINT8_V(rcr, PIIX3State, 4),
>          VMSTATE_END_OF_LIST()
>      }

It would be nice to put this in a subsection, since it should be almost
always 0.

Otherwise, the patch looks good.

Thanks!

Paolo