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Date: Tue, 15 Jan 2013 21:12:28 +0100
From: Laszlo Ersek <lersek@redhat.com>
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Subject: [Qemu-devel] v1->v2 diff (PIIX3: reset the VM when the Reset
 Control Register's RCPU bit gets set)
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To: Laszlo Ersek <lersek@redhat.com>
Cc: blauwirbel@gmail.com, pbonzini@redhat.com, akong@redhat.com, qemu-devel@nongnu.org

diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 75dc9c4..38a1027 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -477,9 +477,26 @@ static void piix3_pre_save(void *opaque)
     }
 }
 
+static bool piix3_rcr_needed(void *opaque)
+{
+    PIIX3State *piix3 = opaque;
+
+    return (piix3->rcr != 0);
+}
+
+static const VMStateDescription vmstate_piix3_rcr = {
+    .name = "PIIX3/rcr",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField []) {
+        VMSTATE_UINT8(rcr, PIIX3State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_piix3 = {
     .name = "PIIX3",
-    .version_id = 4,
+    .version_id = 3,
     .minimum_version_id = 2,
     .minimum_version_id_old = 2,
     .post_load = piix3_post_load,
@@ -488,8 +505,14 @@ static const VMStateDescription vmstate_piix3 = {
         VMSTATE_PCI_DEVICE(dev, PIIX3State),
         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
                               PIIX_NUM_PIRQS, 3),
-        VMSTATE_UINT8_V(rcr, PIIX3State, 4),
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (VMStateSubsection []) {
+        {
+            .vmsd = &vmstate_piix3_rcr,
+            .needed = piix3_rcr_needed,
+        },
+        { 0 }
     }
 };