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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id g18-20020adff3d2000000b00336aac53e75sm2850512wrp.97.2024.01.09.09.13.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jan 2024 09:13:41 -0800 (PST) Message-ID: <50a4ff56-65e5-4c14-86ba-c0759d1c5034@linaro.org> Date: Tue, 9 Jan 2024 18:13:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 1/3] hw/misc: Implement STM32L4x5 EXTI Content-Language: en-US To: =?UTF-8?Q?In=C3=A8s_Varhol?= , qemu-devel@nongnu.org Cc: Paolo Bonzini , Peter Maydell , Thomas Huth , Laurent Vivier , Arnaud Minier , qemu-arm@nongnu.org, Samuel Tardieu , Alistair Francis , Alistair Francis References: <20240109160658.311932-1-ines.varhol@telecom-paris.fr> <20240109160658.311932-2-ines.varhol@telecom-paris.fr> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240109160658.311932-2-ines.varhol@telecom-paris.fr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/1/24 17:06, Inès Varhol wrote: > Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates > more than 32 event/interrupt requests and thus uses more registers > than STM32F4xx EXTI which generates 23 event/interrupt requests. > > Acked-by: Alistair Francis > Signed-off-by: Arnaud Minier > Signed-off-by: Inès Varhol > --- > docs/system/arm/b-l475e-iot01a.rst | 5 +- > hw/misc/Kconfig | 3 + > hw/misc/meson.build | 1 + > hw/misc/stm32l4x5_exti.c | 290 +++++++++++++++++++++++++++++ > hw/misc/trace-events | 5 + > include/hw/misc/stm32l4x5_exti.h | 51 +++++ > 6 files changed, 352 insertions(+), 3 deletions(-) > create mode 100644 hw/misc/stm32l4x5_exti.c > create mode 100644 include/hw/misc/stm32l4x5_exti.h > +static unsigned configurable_mask(unsigned bank) > +{ > + return valid_mask(bank) & ~exti_romask[bank]; > +} Excellent, I'm glad of all the improvement you made over the review process, great work! Reviewed-by: Philippe Mathieu-Daudé > +static void stm32l4x5_exti_write(void *opaque, hwaddr addr, > + uint64_t val64, unsigned int size) > +{ > + Stm32l4x5ExtiState *s = opaque; > + const unsigned bank = regbank_index_by_addr(addr); > + > + trace_stm32l4x5_exti_write(addr, val64); > + > + switch (addr) { > + case EXTI_IMR1: > + case EXTI_IMR2: > + s->imr[bank] = val64 & valid_mask(bank); > + return; > + case EXTI_EMR1: > + case EXTI_EMR2: > + s->emr[bank] = val64 & valid_mask(bank); > + return; > + case EXTI_RTSR1: > + case EXTI_RTSR2: > + s->rtsr[bank] = val64 & configurable_mask(bank); > + return; > + case EXTI_FTSR1: > + case EXTI_FTSR2: > + s->ftsr[bank] = val64 & configurable_mask(bank); > + return; > + case EXTI_SWIER1: > + case EXTI_SWIER2: { > + const uint32_t set = val64 & configurable_mask(bank); > + const uint32_t pend = set & ~s->swier[bank] & s->imr[bank] & > + ~s->pr[bank]; > + s->swier[bank] = set; > + s->pr[bank] |= pend; > + for (unsigned i = 0; i < irqs_per_bank[bank]; i++) { > + if (extract32(pend, i, 1)) { > + qemu_irq_pulse(s->irq[i + 32 * bank]); > + } > + } > + return; > + } [...]