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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v6] riscv: Add support for the Zfa extension Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Jeff Law , Tsukasa OI , liweiwei@iscas.ac.cn, Daniel Henrique Barboza , Liu Zhiwei , Rob Bradford References: <20230630170230.1043454-1-christoph.muellner@vrull.eu> From: Richard Henderson In-Reply-To: <20230630170230.1043454-1-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.095, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/30/23 19:02, Christoph Muellner wrote: > From: Christoph Müllner > > This patch introduces the RISC-V Zfa extension, which introduces > additional floating-point instructions: > * fli (load-immediate) with pre-defined immediates > * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) > * fround/froundmx (round to integer) > * fcvtmod.w.d (Modular Convert-to-Integer) > * fmv* to access high bits of float register bigger than XLEN > * Quiet comparison instructions (fleq/fltq) > > Zfa defines its instructions in combination with the following extensions: > * single-precision floating-point (F) > * double-precision floating-point (D) > * quad-precision floating-point (Q) > * half-precision floating-point (Zfh) > > Since QEMU does not support the RISC-V quad-precision floating-point > ISA extension (Q), this patch does not include the instructions that > depend on this extension. All other instructions are included in this > patch. > > The Zfa specification can be found here: > https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex > The Zfa specifciation is frozen and is in public review since May 3, 2023: > https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg > > The patch also includes a TCG test for the fcvtmod.w.d instruction. > The test cases test for correct results and flag behaviour. > Note, that the Zfa specification requires fcvtmod's flag behaviour > to be identical to a fcvt with the same operands (which is also > tested). > > Signed-off-by: Christoph Müllner > > --- > > This patch depends on float64_to_int64_modulo(), which is provided > by a patchset from Richard Henderson: > https://lists.nongnu.org/archive/html/qemu-devel/2023-05/msg07022.html > > Changes in v6: > * Address issues in trans_fmvp_d_x() and trans_fmvh_x_d() > > Changes in v5: > * Merge all three commits > * Address issues reported by Richard > > Changes in v4: > * Rebase and resolve conflicts > * Fix whitespace issue (thanks Rob) > * Add patch to implemnt fcvtmod.w.d using float64_to_int64_modulo() > * Add (demo) test for fcvtmod.w.d > > Changes in v3: > * Add disassembler support > * Enable Zfa by default > * Remove forgotten comments in the decoder > * Fix fli translation code (use movi instead of ld) > * Tested against SPEC CPU2017 fprate > * Use floatN_[min|max] for f[min|max]m.* instructions > > Changes in v2: > * Remove calls to mark_fs_dirty() in comparison trans functions > * Rewrite fround(nx) using float*_round_to_int() > * Move fli* to translation unit and fix NaN-boxing of NaN values > * Reimplement FCVTMOD.W.D > * Add use of second register in trans_fmvp_d_x() > > disas/riscv.c | 151 +++++++ > target/riscv/cpu.c | 8 + > target/riscv/cpu_cfg.h | 1 + > target/riscv/fpu_helper.c | 154 +++++++ > target/riscv/helper.h | 19 + > target/riscv/insn32.decode | 26 ++ > target/riscv/insn_trans/trans_rvzfa.c.inc | 521 ++++++++++++++++++++++ > target/riscv/translate.c | 1 + > tests/tcg/riscv64/Makefile.target | 6 + > tests/tcg/riscv64/test-fcvtmod.c | 345 ++++++++++++++ > 10 files changed, 1232 insertions(+) > create mode 100644 target/riscv/insn_trans/trans_rvzfa.c.inc > create mode 100644 tests/tcg/riscv64/test-fcvtmod.c Reviewed-by: Richard Henderson r~