From: Richard Henderson <richard.henderson@linaro.org>
To: Harsh Prateek Bora <harshpb@linux.ibm.com>,
Glenn Miles <milesg@linux.ibm.com>,
qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com,
thuth@redhat.com, rathc@linux.ibm.com
Subject: Re: [PATCH v6 7/9] hw/ppc: Support for an IBM PPE42 CPU decrementer
Date: Sun, 28 Sep 2025 12:27:30 -0700 [thread overview]
Message-ID: <50d8690f-d5a9-4cc4-9111-8f2d4e5bfd5f@linaro.org> (raw)
In-Reply-To: <f023d7c8-1556-448b-8cf6-1ee1cc2f7b50@linux.ibm.com>
On 9/28/25 10:51, Harsh Prateek Bora wrote:
>
>
> On 9/26/25 01:47, Glenn Miles wrote:
>> The IBM PPE42 processors support a 32-bit decrementer
>> that can raise an external interrupt when DEC[0]
>> transitions from a 0 to a 1 (a non-negative value to a
>
> I guess it was meant to be 0 to -1 (0xffffffff)?
> No need to re-spin just for that though.
No, Glenn is talking about bit DEC[0], so 0 or 1 only.
r~
next prev parent reply other threads:[~2025-09-28 19:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-25 20:17 [PATCH v6 0/9] Add IBM PPE42 CPU support Glenn Miles
2025-09-25 20:17 ` [PATCH v6 1/9] target/ppc: IBM PPE42 general regs and flags Glenn Miles
2025-09-25 20:17 ` [PATCH v6 2/9] target/ppc: Add IBM PPE42 family of processors Glenn Miles
2025-09-26 15:47 ` Chinmay Rath
2025-09-25 20:17 ` [PATCH v6 3/9] target/ppc: IBM PPE42 exception flags and regs Glenn Miles
2025-09-25 20:17 ` [PATCH v6 4/9] target/ppc: Add IBM PPE42 exception model Glenn Miles
2025-09-25 20:17 ` [PATCH v6 5/9] target/ppc: Support for IBM PPE42 MMU Glenn Miles
2025-09-25 20:17 ` [PATCH v6 6/9] target/ppc: Add IBM PPE42 special instructions Glenn Miles
2025-09-25 20:17 ` [PATCH v6 7/9] hw/ppc: Support for an IBM PPE42 CPU decrementer Glenn Miles
2025-09-28 17:51 ` Harsh Prateek Bora
2025-09-28 19:27 ` Richard Henderson [this message]
2025-09-28 19:33 ` Harsh Prateek Bora
2025-09-25 20:17 ` [PATCH v6 8/9] hw/ppc: Add a test machine for the IBM PPE42 CPU Glenn Miles
2025-09-25 20:17 ` [PATCH v6 9/9] tests/functional: Add test for IBM PPE42 instructions Glenn Miles
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=50d8690f-d5a9-4cc4-9111-8f2d4e5bfd5f@linaro.org \
--to=richard.henderson@linaro.org \
--cc=clg@redhat.com \
--cc=harshpb@linux.ibm.com \
--cc=milesg@linux.ibm.com \
--cc=npiggin@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=rathc@linux.ibm.com \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).