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References: <20190118131456.32451-1-kbastian@mail.uni-paderborn.de>
	<20190118131456.32451-25-kbastian@mail.uni-paderborn.de>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <50d95ed2-d8a4-0a05-f67c-0c18b5e87a33@linaro.org>
Date: Sun, 20 Jan 2019 12:24:44 +1100
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Subject: Re: [Qemu-devel] [PATCH v4 24/35] target/riscv: Move
 gen_arith_imm() decoding into trans_* functions
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To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, sagark@eecs.berkeley.edu, palmer@sifive.com, Alistair.Francis@wdc.com
Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de, qemu-devel@nongnu.org

On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
>  static bool trans_slli(DisasContext *ctx, arg_slli *a)
>  {
> -    gen_arith_imm(ctx, OPC_RISC_SLLI, a->rd, a->rs1, a->shamt);
> +    if (a->rd != 0) {
> +        TCGv t = tcg_temp_new();
> +        gen_get_gpr(t, a->rs1);
> +
> +        if (a->shamt >= TARGET_LONG_BITS) {
> +            return false;
> +        }

I think the shmat test should be first, so that

	slli	r0, r1, 99

produces SIGILL instead of translating to a nop.

>  static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
>  {
> -    gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_IW , a->rd, a->rs1,
> -                  a->shamt | 0x400);
> +    TCGv t = tcg_temp_new();
> +    gen_get_gpr(t, a->rs1);
> +    tcg_gen_sextract_tl(t, t, a->shamt, 32 - a->shamt);
> +    /* sign-extend for W instructions */
> +    tcg_gen_ext32s_tl(t, t);

Sign extension of a sign-extracted value?


r~