From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Date: Wed, 27 Oct 2021 15:02:20 -0700 [thread overview]
Message-ID: <5125d756-1496-bd9a-cce6-83c2d63c6ce6@linaro.org> (raw)
In-Reply-To: <20211027180730.1551932-22-f4bug@amsat.org>
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert 3-register operations to decodetree.
>
> Per the Encoding of Operation Field for 3R Instruction Format'
> (Table 3.25), these instructions are not defined for the BYTE
> format. Therefore the TRANS_DF_iii_b() macro returns 'false'
> in that case, because no such instruction is decoded.
>
> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> v2: TRANS_DF_iii_b() uses array[4]
> ---
> target/mips/tcg/msa.decode | 11 ++
> target/mips/tcg/msa_translate.c | 195 ++++++--------------------------
> 2 files changed, 48 insertions(+), 158 deletions(-)
>
> diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
> index 7201b821ae0..f6471b92fc7 100644
> --- a/target/mips/tcg/msa.decode
> +++ b/target/mips/tcg/msa.decode
> @@ -87,10 +87,21 @@ BNZ 010001 111 .. ..... ................ @bz
> SRARI 011110 010 ....... ..... ..... 001010 @bit
> SRLRI 011110 011 ....... ..... ..... 001010 @bit
>
> + DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
> + DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
> + DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
> + DPADD_U 011110 011.. ..... ..... ..... 010011 @3r
> + DPSUB_S 011110 100.. ..... ..... ..... 010011 @3r
> + DPSUB_U 011110 101.. ..... ..... ..... 010011 @3r
> +
> SLD 011110 000 .. ..... ..... ..... 010100 @3r
> SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
>
> VSHF 011110 000 .. ..... ..... ..... 010101 @3r
> + HADD_S 011110 100.. ..... ..... ..... 010101 @3r
> + HADD_U 011110 101.. ..... ..... ..... 010101 @3r
> + HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
> + HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
>
> FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
> FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
> index c7ca629d684..5cc704c9ace 100644
> --- a/target/mips/tcg/msa_translate.c
> +++ b/target/mips/tcg/msa_translate.c
> @@ -47,13 +47,11 @@ enum {
> OPC_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
> OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
> OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
> - OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
> OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
> OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
> OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
> OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
> OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
> - OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
> OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
> OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
> OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
> @@ -61,7 +59,6 @@ enum {
> OPC_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
> OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
> OPC_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
> - OPC_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13,
> OPC_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
> OPC_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
> OPC_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
> @@ -69,7 +66,6 @@ enum {
> OPC_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
> OPC_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
> OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
> - OPC_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13,
> OPC_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
> OPC_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
> OPC_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
> @@ -77,30 +73,24 @@ enum {
> OPC_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
> OPC_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
> OPC_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
> - OPC_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13,
> OPC_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
> - OPC_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15,
> OPC_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
> OPC_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
> OPC_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
> OPC_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
> OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
> OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
> - OPC_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13,
> OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
> - OPC_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15,
> OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
> OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
> OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
> OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
> OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
> - OPC_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15,
> OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
> OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
> OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
> OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
> OPC_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
> - OPC_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15,
>
> /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
> OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> @@ -257,6 +247,21 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
> #define TRANS_DF_ii(NAME, trans_func, gen_func) \
> TRANS_DF_x(ii, NAME, trans_func, gen_func)
>
> +#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
> + static gen_helper_piii * const NAME##_tab[4] = { \
> + gen_func##_h, gen_func##_w, gen_func##_d \
> + }; \
> + static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
> + { \
> + if (a->df == DF_BYTE) { \
> + return false; \
> + } \
> + if (!check_msa_enabled(ctx)) { \
> + return true; \
> + } \
> + return trans_func(ctx, a, NAME##_tab[a->df - DF_HALF]); \
Either reduce the size of the array by one, or place the NULL in its proper place at the
beginning rather than the end of the array. I think the latter is in the end clearer.
You could just as well place the checks within trans_msa_3r:
if (gen_msa_3r == NULL) {
return false;
}
if (!check_msa_enabled(ctx)) {
return true;
}
r~
next prev parent reply other threads:[~2021-10-27 22:05 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-27 18:06 [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
2021-10-27 18:06 ` [PATCH v2 01/32] target/mips: Fix MSA MADDV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 02/32] target/mips: Fix MSA MSUBV.B opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 03/32] tests/tcg/mips: Run MSA opcodes tests on user-mode emulation Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 04/32] target/mips: Use dup_const() to simplify Philippe Mathieu-Daudé
2021-10-27 19:06 ` Richard Henderson
2021-10-28 20:53 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 05/32] target/mips: Have check_msa_access() return a boolean Philippe Mathieu-Daudé
2021-10-27 19:07 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 06/32] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 07/32] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 08/32] target/mips: Convert MSA LDI opcode to decodetree Philippe Mathieu-Daudé
2021-10-27 19:10 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 09/32] target/mips: Convert MSA I5 instruction format " Philippe Mathieu-Daudé
2021-10-27 19:17 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 10/32] target/mips: Convert MSA BIT " Philippe Mathieu-Daudé
2021-10-27 21:20 ` Richard Henderson
2021-10-28 11:04 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 11/32] target/mips: Convert MSA SHF opcode " Philippe Mathieu-Daudé
2021-10-27 21:21 ` Richard Henderson
2021-10-28 11:45 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 12/32] target/mips: Convert MSA I8 instruction format " Philippe Mathieu-Daudé
2021-10-27 21:31 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 13/32] target/mips: Convert MSA load/store " Philippe Mathieu-Daudé
2021-10-27 21:42 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 14/32] target/mips: Convert MSA 2RF " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 15/32] target/mips: Convert MSA FILL opcode " Philippe Mathieu-Daudé
2021-10-27 21:46 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format " Philippe Mathieu-Daudé
2021-10-27 21:50 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 17/32] target/mips: Convert MSA VEC " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) Philippe Mathieu-Daudé
2021-10-27 21:53 ` Richard Henderson
2021-10-28 13:14 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) Philippe Mathieu-Daudé
2021-10-27 21:54 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) Philippe Mathieu-Daudé
2021-10-27 22:02 ` Richard Henderson [this message]
2021-10-28 13:40 ` Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree Philippe Mathieu-Daudé
2021-10-27 22:05 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode " Philippe Mathieu-Daudé
2021-10-27 22:08 ` Richard Henderson
2021-10-27 18:07 ` [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 28/32] target/mips: Convert CFCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 29/32] target/mips: Convert CTCMSA " Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 30/32] target/mips: Remove generic MSA opcode Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group Philippe Mathieu-Daudé
2021-10-27 18:07 ` [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init() Philippe Mathieu-Daudé
2021-10-27 18:12 ` [PATCH v2 00/32] target/mips: Fully convert MSA opcodes to decodetree Philippe Mathieu-Daudé
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