From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCTI6-0001lH-9X for qemu-devel@nongnu.org; Mon, 04 Mar 2013 06:10:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCTI4-0007fp-0F for qemu-devel@nongnu.org; Mon, 04 Mar 2013 06:10:46 -0500 Received: from cantor2.suse.de ([195.135.220.15]:38631 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCTI3-0007fl-Jl for qemu-devel@nongnu.org; Mon, 04 Mar 2013 06:10:43 -0500 Message-ID: <51348131.8020703@suse.de> Date: Mon, 04 Mar 2013 12:10:41 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1361900421-28354-1-git-send-email-peter.maydell@linaro.org> <1361900421-28354-8-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1361900421-28354-8-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v7 07/11] hw/arm_gic: Convert ARM GIC classes to use init/realize List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: kvm@vger.kernel.org, Gleb Natapov , patches@linaro.org, Marcelo Tosatti , qemu-devel@nongnu.org, Blue Swirl , Paolo Bonzini , kvmarm@lists.cs.columbia.edu Am 26.02.2013 18:40, schrieb Peter Maydell: > Convert the ARM GIC classes to use init/realize rather than > SysBusDevice::init. (We have to do them all in one patch to > avoid unconverted subclasses calling a nonexistent SysBusDevice > init function in the base class and crashing.) >=20 > Signed-off-by: Peter Maydell > --- > hw/arm_gic.c | 23 +++++++++++++---------- > hw/arm_gic_common.c | 26 +++++++++++++++----------- > hw/arm_gic_internal.h | 2 +- > hw/armv7m_nvic.c | 15 ++++++++------- > 4 files changed, 37 insertions(+), 29 deletions(-) >=20 > diff --git a/hw/arm_gic.c b/hw/arm_gic.c > index 90e43d0..250e720 100644 > --- a/hw/arm_gic.c > +++ b/hw/arm_gic.c > @@ -659,14 +659,18 @@ void gic_init_irqs_and_distributor(GICState *s, i= nt num_irq) > memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1= 000); > } > =20 > -static int arm_gic_init(SysBusDevice *dev) > +static void arm_gic_realize(DeviceState *dev, Error **errp) > { > - /* Device instance init function for the GIC sysbus device */ > + /* Device instance realize function for the GIC sysbus device */ > int i; > - GICState *s =3D FROM_SYSBUS(GICState, dev); > + GICState *s =3D ARM_GIC(dev); > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); > ARMGICClass *agc =3D ARM_GIC_GET_CLASS(s); > =20 > - agc->parent_init(dev); > + agc->parent_realize(dev, errp); > + if (error_is_set(errp)) { > + return; > + } > =20 > gic_init_irqs_and_distributor(s, s->num_irq); > =20 > @@ -686,22 +690,21 @@ static int arm_gic_init(SysBusDevice *dev) > "gic_cpu", 0x100); > } > /* Distributor */ > - sysbus_init_mmio(dev, &s->iomem); > + sysbus_init_mmio(sbd, &s->iomem); > /* cpu interfaces (one for "current cpu" plus one per cpu) */ > for (i =3D 0; i <=3D NUM_CPU(s); i++) { > - sysbus_init_mmio(dev, &s->cpuiomem[i]); > + sysbus_init_mmio(sbd, &s->cpuiomem[i]); > } > - return 0; > } > =20 > static void arm_gic_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > - SysBusDeviceClass *sbc =3D SYS_BUS_DEVICE_CLASS(klass); > ARMGICClass *agc =3D ARM_GIC_CLASS(klass); > - agc->parent_init =3D sbc->init; > - sbc->init =3D arm_gic_init; > + > dc->no_user =3D 1; > + agc->parent_realize =3D dc->realize; > + dc->realize =3D arm_gic_realize; > } > =20 > static const TypeInfo arm_gic_info =3D { > diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c > index 2947622..3b2955c 100644 > --- a/hw/arm_gic_common.c > +++ b/hw/arm_gic_common.c > @@ -104,31 +104,35 @@ static int gic_load(QEMUFile *f, void *opaque, in= t version_id) > return 0; > } > =20 > -static int arm_gic_common_init(SysBusDevice *dev) > +static void arm_gic_common_realize(DeviceState *dev, Error **errp) > { > - GICState *s =3D FROM_SYSBUS(GICState, dev); > + GICState *s =3D ARM_GIC_COMMON(dev); > int num_irq =3D s->num_irq; > =20 > if (s->num_cpu > NCPU) { > - hw_error("requested %u CPUs exceeds GIC maximum %d\n", > - s->num_cpu, NCPU); > + error_setg(errp, "requested %u CPUs exceeds GIC maximum %d\n", Please drop \n for error_setg(). Probably would be worth adding to a convert-to-realize section on the Wiki. > + s->num_cpu, NCPU); > + return; > } > s->num_irq +=3D GIC_BASE_IRQ; > if (s->num_irq > GIC_MAXIRQ) { > - hw_error("requested %u interrupt lines exceeds GIC maximum %d\= n", > - num_irq, GIC_MAXIRQ); > + error_setg(errp, > + "requested %u interrupt lines exceeds GIC maximum %= d\n", > + num_irq, GIC_MAXIRQ); > + return; > } > /* ITLinesNumber is represented as (N / 32) - 1 (see > * gic_dist_readb) so this is an implementation imposed > * restriction, not an architectural one: > */ > if (s->num_irq < 32 || (s->num_irq % 32)) { > - hw_error("%d interrupt lines unsupported: not divisible by 32\= n", > - num_irq); > + error_setg(errp, > + "%d interrupt lines unsupported: not divisible by 3= 2\n", > + num_irq); > + return; > } > =20 > register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); > - return 0; > } > =20 > static void arm_gic_common_reset(DeviceState *dev) > @@ -173,12 +177,12 @@ static Property arm_gic_common_properties[] =3D { > =20 > static void arm_gic_common_class_init(ObjectClass *klass, void *data) > { > - SysBusDeviceClass *sc =3D SYS_BUS_DEVICE_CLASS(klass); > DeviceClass *dc =3D DEVICE_CLASS(klass); > + > dc->reset =3D arm_gic_common_reset; > + dc->realize =3D arm_gic_common_realize; > dc->props =3D arm_gic_common_properties; > dc->no_user =3D 1; > - sc->init =3D arm_gic_common_init; > } > =20 > static const TypeInfo arm_gic_common_type =3D { > diff --git a/hw/arm_gic_internal.h b/hw/arm_gic_internal.h > index 3640be0..3ba37f3 100644 > --- a/hw/arm_gic_internal.h > +++ b/hw/arm_gic_internal.h > @@ -132,7 +132,7 @@ typedef struct ARMGICCommonClass { > =20 > typedef struct ARMGICClass { > ARMGICCommonClass parent_class; > - int (*parent_init)(SysBusDevice *dev); > + DeviceRealize parent_realize; > } ARMGICClass; > =20 > #endif /* !QEMU_ARM_GIC_INTERNAL_H */ > diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c > index d5798d0..3c79674 100644 > --- a/hw/armv7m_nvic.c > +++ b/hw/armv7m_nvic.c > @@ -41,7 +41,7 @@ typedef struct NVICClass { > /*< private >*/ > ARMGICClass parent_class; > /*< public >*/ > - int (*parent_init)(SysBusDevice *dev); > + DeviceRealize parent_realize; > void (*parent_reset)(DeviceState *dev); > } NVICClass; > =20 > @@ -465,7 +465,7 @@ static void armv7m_nvic_reset(DeviceState *dev) > systick_reset(s); > } > =20 > -static int armv7m_nvic_init(SysBusDevice *dev) > +static void armv7m_nvic_realize(DeviceState *dev, Error **errp) > { > nvic_state *s =3D NVIC(dev); > NVICClass *nc =3D NVIC_GET_CLASS(s); > @@ -475,7 +475,10 @@ static int armv7m_nvic_init(SysBusDevice *dev) > /* Tell the common code we're an NVIC */ > s->gic.revision =3D 0xffffffff; > s->num_irq =3D s->gic.num_irq; > - nc->parent_init(dev); > + nc->parent_realize(dev, errp); > + if (error_is_set(errp)) { > + return; > + } > gic_init_irqs_and_distributor(&s->gic, s->num_irq); > /* The NVIC and system controller register area looks like this: > * 0..0xff : system control registers, including systick > @@ -503,7 +506,6 @@ static int armv7m_nvic_init(SysBusDevice *dev) > */ > memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->c= ontainer); > s->systick.timer =3D qemu_new_timer_ns(vm_clock, systick_timer_tic= k, s); > - return 0; > } > =20 > static void armv7m_nvic_instance_init(Object *obj) > @@ -526,13 +528,12 @@ static void armv7m_nvic_class_init(ObjectClass *k= lass, void *data) > { > NVICClass *nc =3D NVIC_CLASS(klass); > DeviceClass *dc =3D DEVICE_CLASS(klass); > - SysBusDeviceClass *sdc =3D SYS_BUS_DEVICE_CLASS(klass); > =20 > nc->parent_reset =3D dc->reset; > - nc->parent_init =3D sdc->init; > - sdc->init =3D armv7m_nvic_init; > + nc->parent_realize =3D dc->realize; > dc->vmsd =3D &vmstate_nvic; > dc->reset =3D armv7m_nvic_reset; > + dc->realize =3D armv7m_nvic_realize; > } > =20 > static const TypeInfo armv7m_nvic_info =3D { >=20 Otherwise looks fine, thanks. Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg