From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCwXj-0003mO-AR for qemu-devel@nongnu.org; Tue, 05 Mar 2013 13:24:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCwDP-0002jQ-3F for qemu-devel@nongnu.org; Tue, 05 Mar 2013 13:07:06 -0500 Received: from mx1.redhat.com ([209.132.183.28]:2759) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCwDO-0002jE-RR for qemu-devel@nongnu.org; Tue, 05 Mar 2013 13:03:51 -0500 Message-ID: <51363400.9070001@redhat.com> Date: Tue, 05 Mar 2013 19:05:52 +0100 From: Laszlo Ersek MIME-Version: 1.0 References: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> <1362495898-15352-3-git-send-email-pbonzini@redhat.com> In-Reply-To: <1362495898-15352-3-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/3] pc: port 92 reset requires a low->high transition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: aliguori@us.ibm.com, dwmw2@infradead.org, qemu-devel@nongnu.org On 03/05/13 16:04, Paolo Bonzini wrote: > The PIIX datasheet says that "before another INIT pulse can be > generated via [port 92h], [bit 0] must be written back to a > zero. > > This bug is masked right now because a full reset will clear the > value of port 92h. But once we implement soft reset correctly, > the next attempt to enable the A20 line by setting bit 1 (and > leaving the others untouched) will cause another reset. > > Signed-off-by: Paolo Bonzini > --- > hw/pc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/pc.c b/hw/pc.c > index 07caba7..523db1f 100644 > --- a/hw/pc.c > +++ b/hw/pc.c > @@ -435,11 +435,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, > unsigned size) > { > Port92State *s = opaque; > + int oldval = s->outport; > > DPRINTF("port92: write 0x%02x\n", val); > s->outport = val; > qemu_set_irq(*s->a20_out, (val >> 1) & 1); > - if (val & 1) { > + if ((val & 1) && !(oldval & 1)) { > qemu_system_reset_request(); > } > } > Reviewed-by: Laszlo Ersek