From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:36634) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCxFg-0001q3-4E for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:10:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCxFd-0000RI-GO for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:10:16 -0500 Received: from mx1.redhat.com ([209.132.183.28]:19345) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCxFd-0000Hf-7L for qemu-devel@nongnu.org; Tue, 05 Mar 2013 14:10:13 -0500 Message-ID: <51364381.902@redhat.com> Date: Tue, 05 Mar 2013 20:12:01 +0100 From: Laszlo Ersek MIME-Version: 1.0 References: <1362499403-16514-1-git-send-email-pbonzini@redhat.com> <1362502791.32301.13.camel@i7.infradead.org> In-Reply-To: <1362502791.32301.13.camel@i7.infradead.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 4/3] wakeup: only reset the CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Woodhouse Cc: Paolo Bonzini , aliguori@us.ibm.com, seabios , qemu-devel@nongnu.org On 03/05/13 17:59, David Woodhouse wrote:> On Tue, 2013-03-05 at 17:03 +0100, Paolo Bonzini wrote: >> Resuming from suspend-to-RAM should not reset all devices. Only the >> CPU should get a reset signal. > > Hm... on reflection, I don't actually know if this is true. > > Perhaps we *should* reset all devices. After all, in a real machine > they'll all have been turned off and the RAM will have been in > self-refresh. Surely they have to be reset? > > So maybe we should *let* the i440FX PAM registers get reset to point to > ROM. And fix the firmware to *cope* with that, check to see if the > shadow RAM already holds an image of a started-up firmware with the > correct checksum, and jump back to it. > > That is: perhaps it's a *SeaBIOS* bug that suspend/resume doesn't work > if the PAM configuration is reset? I think it is indeed a problem with SeaBIOS. (git.seabios.org (80.81.252.135) seems to be down ATM, so I can only check at f465e1ec.) Open romlayout.S: 622 reset_vector: 623 ljmpw $SEG_BIOS, $entry_post 537 entry_post: 538 cmpl $0, %cs:HaveRunPost // Check for resume/reboot 539 jnz entry_resume 540 ENTRY_INTO32 _cfunc32flat_handle_post // Normal entry point 239 entry_resume: ... 248 // Call handler. 249 jmp handle_resume handle_resume() [src/resume.c] inb_cmos(CMOS_RESET_CODE) It checks the CMOS only after looking at HaveRunPost. The value of HaveRunPost depends on the PAM settings. It's always 0 in ROM, in which case we continue at handle_post() [src/post.c]. Laszlo