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Date: Wed, 06 Mar 2013 13:19:54 +0100
From: Paolo Bonzini <pbonzini@redhat.com>
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Subject: Re: [Qemu-devel] [PATCH v2 1/3] cpu: make CPU_INTERRUPT_RESET
 available on all targets
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>, lersek@redhat.com, aliguori@us.ibm.com, qemu-devel@nongnu.org, dwmw2@infradead.org, afaerber@suse.de

Il 06/03/2013 13:12, Peter Maydell ha scritto:
> On 6 March 2013 17:13, Paolo Bonzini <pbonzini@redhat.com> wrote:
>> Il 06/03/2013 03:02, Peter Crosthwaite ha scritto:
>>> If you truly have connectivity from device land to the CPU cluster
>>> should that be reflected by some sort of QOM linkage?
>>
>> I think in real hardware what happens is that a single "wire" is
>> distributed to all CPUs.  Devices do not have direct links to all the
>> CPUs, they are agnostic of how many CPUs they control (at least on x86).
> 
> This is definitely x86 specific. On ARM, typically each core
> has its own reset line and the only way to reset all cores is
> to assert all the lines.

Each core has indeed its own reset line, but there is only one output
pin for reset in the southbridge (which is where the reset port lies).

Paolo

> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407i/BABGCECJ.html
> lists all the reset inputs for an A9MP, for example.
> 
> -- PMM
> 
>