Re: [Qemu-devel] [PATCH uq/master 2/2] kvm: forward INIT signals coming from the chipset

[Paolo Bonzini <pbonzini@redhat.com>]

Il 10/03/2013 16:24, Gleb Natapov ha scritto:
> On Sun, Mar 10, 2013 at 04:04:39PM +0100, Paolo Bonzini wrote:
>> Il 10/03/2013 15:55, Gleb Natapov ha scritto:
>>>>> Why not move INIT case from below as is? Vcpu is reset to correct sate
>>>>> by QEMU just like during system_reset.
>>>>
>>>> APs would not be able to receive SIPIs after executing do_cpu_init,
>>>> because they would stay in KVM_MP_STATE_RUNNABLE state.
>>>
>>> If APs are in runnable state after reset with in kernel irq chip we
>>> have a bug somewhere.
>>
>> Here is where we are resetting the processor.  After clearing
>> CPU_INTERRUPT_INIT, no matter what else we do (such as resetting the
>> APIC and CPU), we need to set the mp_state to KVM_MP_STATE_INIT_RECEIVED.
>>
>> Or if we go with your simpler hypervisor patch, we need to go to either
>> KVM_MP_STATE_INIT_RECEIVED for APs (wait for SIPI) or
>> KVM_MP_STATE_SIPI_RECEIVED for the BSP (restart running from the reset
>> vector).
>>
> No need for KVM_MP_STATE_SIPI_RECEIVED. Just make it RUNNING. This is similar to
> system_reset path, not? UNINIT for AP, RUNNING for BSP.
> 
>>> Should AP be able to get SIPI without INIT after trigger of INIT# line?
>>
>> Yes, the effect is the same for an INIT interrupt and the triggering of
>> INIT#.
>>
> Can you give me SDM pointer?

10.4.7.3 Local APIC State After an INIT Reset (“Wait-for-SIPI” State)

An INIT reset of the processor can be initiated in either of two ways:

• By asserting the processor’s INIT# pin.

• By sending the processor an INIT IPI (an IPI with the delivery mode
set to INIT).

Upon receiving an INIT through either of these mechanisms, the processor
responds by beginning the initialization process of the processor core
and the local APIC. The state of the local APIC following an INIT reset
is the same as it is after a power-up or
hardware RESET, except that the APIC ID and arbitration ID registers are
not affected. This state is also referred to at the “wait-for-SIPI”
state (see also: Section 8.4.2, “MP Initialization Protocol Requirements
and Restrictions”).

Paolo