From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:52335) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UHdLY-0006Nc-2P for qemu-devel@nongnu.org; Mon, 18 Mar 2013 12:55:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UHdLV-0001XP-0e for qemu-devel@nongnu.org; Mon, 18 Mar 2013 12:55:39 -0400 Received: from cantor2.suse.de ([195.135.220.15]:54664 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UHdLU-0001WV-MC for qemu-devel@nongnu.org; Mon, 18 Mar 2013 12:55:36 -0400 Message-ID: <51474703.4070406@suse.de> Date: Mon, 18 Mar 2013 17:55:31 +0100 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1361775217-3454-1-git-send-email-xudong.hao@intel.com> <20130227105024.GB13054@redhat.com> <403610A45A2B5242BD291EDAE8B37D300FFAFF2A@SHSMSX102.ccr.corp.intel.com> In-Reply-To: <403610A45A2B5242BD291EDAE8B37D300FFAFF2A@SHSMSX102.ccr.corp.intel.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2] piix: define a TOM register to report the base of PCI List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Hao, Xudong" Cc: "aliguori@us.ibm.com" , "stefano.stabellini@eu.citrix.com" , "Michael S. Tsirkin" , "qemu-devel@nongnu.org" , "xen-devel@lists.xen.org" , "JBeulich@suse.com" Am 18.03.2013 16:21, schrieb Hao, Xudong: >> -----Original Message----- >> From: Michael S. Tsirkin [mailto:mst@redhat.com] >> Sent: Wednesday, February 27, 2013 6:50 PM >> To: Hao, Xudong >> Cc: aliguori@us.ibm.com; qemu-devel@nongnu.org; >> stefano.stabellini@eu.citrix.com; xen-devel@lists.xen.org; afaerber@su= se.de; >> JBeulich@suse.com; Zhang, Xiantao >> Subject: Re: [PATCH v2] piix: define a TOM register to report the base= of PCI >> >> On Mon, Feb 25, 2013 at 02:53:37PM +0800, Xudong Hao wrote: >>> v2: >>> * Use "piix: " in the subject rather than "qemu: " >>> * Define TOM register as one byte >>> * Define default TOM value instead of hardcode 0xe0000000 in more tha= t one >> place >>> * Use API pci_set_byte for pci config access >>> * Use dev->config instead of the indirect d->dev.config >>> >>> Define a TOM(top of memory) register to report the base of PCI memory= , >> update >>> memory region dynamically. TOM register are defined to one byte in PC= I >> configure >>> space, because that only upper 4 bit of PCI memory takes effect for X= en, so >>> it requires bios set TOM with 16M-aligned. >>> >>> Signed-off-by: Xudong Hao >>> Signed-off-by: Xiantao Zhang >> >> Could you supply some motivation for this patch? >> >=20 > It's a fix for Xen. Qemu want more information from Xen, copy Stefano's= comments: >=20 > QEMU needs to know where the end of the guest's RAM is (because there i= s > where it allocates the videoram and other stuff), so at least the size > of the MMIO hole is important. Could you please reply to Anthony's comment that this information is already available via fw_cfg interface? hw/fw_cfg.h is designed so that it can be embedded elsewhere (e.g., in SeaBIOS and OpenBIOS). Reusing any information available through that interface would seem much easier than fiddling with reserved registers on emulated hardware. Regards, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg