[Qemu-devel] [PATCH V2 0/3] ARM: Misc ARM big-endian bug fixes

[Qemu-devel] [PATCH V2 0/3] ARM: Misc ARM big-endian bug fixes

[Fabien Chouteau]

v2:
  - I drop the the CPSR.E/SCTLR.E/SCTLR.IE patch. The issue is still too
  complex for me to submit a good patch.

  - Fix the GDB byte order for 64bits registers

Fabien Chouteau (3):
  QAPI: Add ARMEB target-type
  Add default config for armeb-softmmu
  target-arm: Fix VFP register byte order in GDB remote

 default-configs/armeb-softmmu.mak |    3 +++
 qapi-schema.json                  |    9 +++++----
 target-arm/helper.c               |   23 ++++++++++++++++-------
 3 files changed, 24 insertions(+), 11 deletions(-)
 create mode 100644 default-configs/armeb-softmmu.mak

-- 
1.7.9.5

[Qemu-devel] [PATCH V2 1/3] QAPI: Add ARMEB target-type

[Fabien Chouteau]

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
 qapi-schema.json |    9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/qapi-schema.json b/qapi-schema.json
index 28b070f..0615715 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -2993,10 +2993,11 @@
 # Since: 1.2.0
 ##
 { 'enum': 'TargetType',
-  'data': [ 'alpha', 'arm', 'cris', 'i386', 'lm32', 'm68k', 'microblazeel',
-            'microblaze', 'mips64el', 'mips64', 'mipsel', 'mips', 'or32',
-            'ppc64', 'ppcemb', 'ppc', 's390x', 'sh4eb', 'sh4', 'sparc64',
-            'sparc', 'unicore32', 'x86_64', 'xtensaeb', 'xtensa' ] }
+  'data': [ 'alpha', 'arm', 'armeb','cris', 'i386', 'lm32', 'm68k',
+            'microblazeel', 'microblaze', 'mips64el', 'mips64', 'mipsel',
+            'mips', 'or32', 'ppc64', 'ppcemb', 'ppc', 's390x', 'sh4eb',
+            'sh4', 'sparc64', 'sparc', 'unicore32', 'x86_64', 'xtensaeb',
+            'xtensa' ] }
 
 ##
 # @TargetInfo:
-- 
1.7.9.5

[Qemu-devel] [PATCH V2 2/3] Add default config for armeb-softmmu

[Fabien Chouteau]

Just create one that includes arm-softmmu.mak.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
 default-configs/armeb-softmmu.mak |    3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 default-configs/armeb-softmmu.mak

diff --git a/default-configs/armeb-softmmu.mak b/default-configs/armeb-softmmu.mak
new file mode 100644
index 0000000..17670c0
--- /dev/null
+++ b/default-configs/armeb-softmmu.mak
@@ -0,0 +1,3 @@
+# Default configuration for armeb-softmmu
+
+include arm-softmmu.mak
-- 
1.7.9.5

[Qemu-devel] [PATCH V2 3/3] target-arm: Fix VFP register byte order in GDB remote

[Fabien Chouteau]

>From GDB Remote Serial Protocol doc:

"The bytes with the register are transmitted in target byte order."

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
 target-arm/helper.c |   23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index e97e1a5..1ba25e1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -16,18 +16,22 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
 {
     int nregs;
 
-    /* VFP data registers are always little-endian.  */
     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
     if (reg < nregs) {
-        stfq_le_p(buf, env->vfp.regs[reg]);
+        stfq_p(buf, env->vfp.regs[reg]);
         return 8;
     }
     if (arm_feature(env, ARM_FEATURE_NEON)) {
         /* Aliases for Q regs.  */
         nregs += 16;
         if (reg < nregs) {
-            stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
-            stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
+#ifdef TARGET_WORDS_BIGENDIAN
+            stfq_p(buf, env->vfp.regs[(reg - 32) * 2 + 1]);
+            stfq_p(buf + 8, env->vfp.regs[(reg - 32) * 2]);
+#else
+            stfq_p(buf, env->vfp.regs[(reg - 32) * 2]);
+            stfq_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
+#endif  /* TARGET_WORDS_BIGENDIAN */
             return 16;
         }
     }
@@ -45,14 +49,19 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 
     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
     if (reg < nregs) {
-        env->vfp.regs[reg] = ldfq_le_p(buf);
+        env->vfp.regs[reg] = ldfq_p(buf);
         return 8;
     }
     if (arm_feature(env, ARM_FEATURE_NEON)) {
         nregs += 16;
         if (reg < nregs) {
-            env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
-            env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
+#ifdef TARGET_WORDS_BIGENDIAN
+            env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_p(buf);
+            env->vfp.regs[(reg - 32) * 2] = ldfq_p(buf + 8);
+#else
+            env->vfp.regs[(reg - 32) * 2] = ldfq_p(buf);
+            env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_p(buf + 8);
+#endif  /* TARGET_WORDS_BIGENDIAN */
             return 16;
         }
     }
-- 
1.7.9.5

Re: [Qemu-devel] [PATCH V2 0/3] ARM: Misc ARM big-endian bug fixes

[Peter Maydell]

On 19 March 2013 11:21, Fabien Chouteau <chouteau@adacore.com> wrote:
> v2:
>   - I drop the the CPSR.E/SCTLR.E/SCTLR.IE patch. The issue is still too
>   complex for me to submit a good patch.
>
>   - Fix the GDB byte order for 64bits registers
>
> Fabien Chouteau (3):
>   QAPI: Add ARMEB target-type
>   Add default config for armeb-softmmu

Hi Fabien. I'm afraid I don't want to take these two unless they
come attached to an actual cpu and board model that use them.
Otherwise they're really just half-a-feature, I think.

(As an aside, perhaps we should generate the list in qapi-schema.json
automatically rather than hardcoding every target name? dunno)

>   target-arm: Fix VFP register byte order in GDB remote

This one could go in (assuming it passes code review, I
haven't looked too closely yet), because it's just fixing
generic bigendian support.

thanks
-- PMM

Re: [Qemu-devel] [PATCH V2 0/3] ARM: Misc ARM big-endian bug fixes

[Richard Henderson]

On 03/19/2013 04:30 AM, Peter Maydell wrote:
> (As an aside, perhaps we should generate the list in qapi-schema.json
> automatically rather than hardcoding every target name? dunno)

Definitely.  It took me quite a while to find this when updating my
spu target emulator a while back.


r~

Re: [Qemu-devel] [PATCH V2 0/3] ARM: Misc ARM big-endian bug fixes

[Fabien Chouteau]

On 03/19/2013 12:30 PM, Peter Maydell wrote:
> On 19 March 2013 11:21, Fabien Chouteau <chouteau@adacore.com> wrote:
>> v2:
>>   - I drop the the CPSR.E/SCTLR.E/SCTLR.IE patch. The issue is still too
>>   complex for me to submit a good patch.
>>
>>   - Fix the GDB byte order for 64bits registers
>>
>> Fabien Chouteau (3):
>>   QAPI: Add ARMEB target-type
>>   Add default config for armeb-softmmu
> 
> Hi Fabien. I'm afraid I don't want to take these two unless they
> come attached to an actual cpu and board model that use them.
> Otherwise they're really just half-a-feature, I think.
>

Well these patches are very small, but I think it can help people to get
started. I submitted them because I thought it was a regression to not
be able to build qemu-system-armeb.

Regards,

-- 
Fabien Chouteau

Re: [Qemu-devel] [PATCH V2 0/3] ARM: Misc ARM big-endian bug fixes

[Peter Maydell]

On 20 March 2013 09:28, Fabien Chouteau <chouteau@adacore.com> wrote:
> On 03/19/2013 12:30 PM, Peter Maydell wrote:
>> On 19 March 2013 11:21, Fabien Chouteau <chouteau@adacore.com> wrote:
>>> Fabien Chouteau (3):
>>>   QAPI: Add ARMEB target-type
>>>   Add default config for armeb-softmmu
>>
>> Hi Fabien. I'm afraid I don't want to take these two unless they
>> come attached to an actual cpu and board model that use them.
>> Otherwise they're really just half-a-feature, I think.
>>
>
> Well these patches are very small, but I think it can help people to get
> started. I submitted them because I thought it was a regression to not
> be able to build qemu-system-armeb.

No, we deliberately don't build qemu-system-armeb because we
don't have any implemented machines which are big-endian ARM.
When the first machine is added to QEMU the patch set adding
that support should turn on building of qemu-system-armeb
(which would then support just that one machine type).

thanks
-- PMM