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Date: Wed, 20 Mar 2013 18:26:27 +0100
From: Fabien Chouteau <chouteau@adacore.com>
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Subject: Re: [Qemu-devel] Cortex-M4F Floating Point system registers
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>

On 03/20/2013 05:43 PM, Peter Maydell wrote:
> On 20 March 2013 16:05, Fabien Chouteau <chouteau@adacore.com> wrote:
>> I'm looking at the ARMv7-M profile and the implementation in QEMU.
>> Looks like M3 is supported and I'd like to work on M4F (FP context save
>> and lazy FP context save).
>
> This is going to be interesting because we don't currently have
> any mechanisms implemented for 'trap on attempt to use FP insn'.
> (Not impossible, just the code isn't there at the moment.)
>

OK, if you can give me any insight of what needs to be done for M4F and
how should I do it, don't hesitate.

>> I wonder how the FPU system registers, and more generally how the
>> co-processor registers are implemented in QEMU.
>>
>> For example in the Cortex-M4 TRM it seems like FP system registers are
>> mapped in memory. I don't see that implemented in QEMU.
>
> Yes, M profile maps lots of sysregs in memory. Mostly we implement
> these in hw/armv7m_nvic.c. It's kind of ugly the way that code
> reaches into the CPU implementation though.
>

Thanks, I'll take a look at this.

-- 
Fabien Chouteau