* [Qemu-devel] Cortex-M4F Floating Point system registers
@ 2013-03-20 16:05 Fabien Chouteau
2013-03-20 16:43 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: Fabien Chouteau @ 2013-03-20 16:05 UTC (permalink / raw)
To: qemu-devel@nongnu.org
Hello QEMU ARM folks,
I'm looking at the ARMv7-M profile and the implementation in QEMU.
Looks like M3 is supported and I'd like to work on M4F (FP context save
and lazy FP context save).
I wonder how the FPU system registers, and more generally how the
co-processor registers are implemented in QEMU.
For example in the Cortex-M4 TRM it seems like FP system registers are
mapped in memory. I don't see that implemented in QEMU.
Thanks,
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] Cortex-M4F Floating Point system registers
2013-03-20 16:05 [Qemu-devel] Cortex-M4F Floating Point system registers Fabien Chouteau
@ 2013-03-20 16:43 ` Peter Maydell
2013-03-20 17:26 ` Fabien Chouteau
0 siblings, 1 reply; 3+ messages in thread
From: Peter Maydell @ 2013-03-20 16:43 UTC (permalink / raw)
To: Fabien Chouteau; +Cc: qemu-devel@nongnu.org
On 20 March 2013 16:05, Fabien Chouteau <chouteau@adacore.com> wrote:
> I'm looking at the ARMv7-M profile and the implementation in QEMU.
> Looks like M3 is supported and I'd like to work on M4F (FP context save
> and lazy FP context save).
This is going to be interesting because we don't currently have
any mechanisms implemented for 'trap on attempt to use FP insn'.
(Not impossible, just the code isn't there at the moment.)
> I wonder how the FPU system registers, and more generally how the
> co-processor registers are implemented in QEMU.
>
> For example in the Cortex-M4 TRM it seems like FP system registers are
> mapped in memory. I don't see that implemented in QEMU.
Yes, M profile maps lots of sysregs in memory. Mostly we implement
these in hw/armv7m_nvic.c. It's kind of ugly the way that code
reaches into the CPU implementation though.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] Cortex-M4F Floating Point system registers
2013-03-20 16:43 ` Peter Maydell
@ 2013-03-20 17:26 ` Fabien Chouteau
0 siblings, 0 replies; 3+ messages in thread
From: Fabien Chouteau @ 2013-03-20 17:26 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel@nongnu.org
On 03/20/2013 05:43 PM, Peter Maydell wrote:
> On 20 March 2013 16:05, Fabien Chouteau <chouteau@adacore.com> wrote:
>> I'm looking at the ARMv7-M profile and the implementation in QEMU.
>> Looks like M3 is supported and I'd like to work on M4F (FP context save
>> and lazy FP context save).
>
> This is going to be interesting because we don't currently have
> any mechanisms implemented for 'trap on attempt to use FP insn'.
> (Not impossible, just the code isn't there at the moment.)
>
OK, if you can give me any insight of what needs to be done for M4F and
how should I do it, don't hesitate.
>> I wonder how the FPU system registers, and more generally how the
>> co-processor registers are implemented in QEMU.
>>
>> For example in the Cortex-M4 TRM it seems like FP system registers are
>> mapped in memory. I don't see that implemented in QEMU.
>
> Yes, M profile maps lots of sysregs in memory. Mostly we implement
> these in hw/armv7m_nvic.c. It's kind of ugly the way that code
> reaches into the CPU implementation though.
>
Thanks, I'll take a look at this.
--
Fabien Chouteau
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2013-03-20 17:26 UTC | newest]
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2013-03-20 16:05 [Qemu-devel] Cortex-M4F Floating Point system registers Fabien Chouteau
2013-03-20 16:43 ` Peter Maydell
2013-03-20 17:26 ` Fabien Chouteau
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