From: Fabien Chouteau <chouteau@adacore.com>
To: Alexander Graf <agraf@suse.de>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH] PPC: init_excp_7x0: fix hreset entry point.
Date: Wed, 27 Mar 2013 17:11:06 +0100 [thread overview]
Message-ID: <51531A1A.1010107@adacore.com> (raw)
In-Reply-To: <51531522.2060402@adacore.com>
On 03/27/2013 04:49 PM, Fabien Chouteau wrote:
> On 03/27/2013 04:10 PM, Alexander Graf wrote:
>>> It's actually already implemented (helper_regs.h:96). The question is:
>>> what is the value of MSR[IP] at reset?
>>
>> For 740 / 750, it's 1. All other bits are 0.
>
> Is it true for all PPC, because MSR_EP/IP is set for all kind of CPU right now.
>
Well, when the msr_maks allows it...
--
Fabien Chouteau
prev parent reply other threads:[~2013-03-27 16:11 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-27 13:50 [Qemu-devel] [PATCH] PPC: init_excp_7x0: fix hreset entry point Fabien Chouteau
2013-03-27 13:54 ` Alexander Graf
2013-03-27 14:00 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-03-27 14:04 ` Alexander Graf
2013-03-27 14:59 ` Fabien Chouteau
2013-03-27 15:09 ` Fabien Chouteau
2013-03-27 15:10 ` Alexander Graf
2013-03-27 15:49 ` Fabien Chouteau
2013-03-27 16:07 ` Alexander Graf
2013-03-27 16:17 ` Fabien Chouteau
2013-03-27 16:22 ` Alexander Graf
2013-03-27 16:49 ` Fabien Chouteau
2013-03-27 16:11 ` Fabien Chouteau [this message]
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