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([2607:fb90:46a:1099:e682:8d73:3200:dae5]) by smtp.gmail.com with ESMTPSA id n13-20020a170903110d00b0015e8d4eb292sm2026628plh.220.2022.05.13.08.47.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 May 2022 08:47:40 -0700 (PDT) Message-ID: <51639c5c-9092-c4a2-c215-2cbdf110d347@linaro.org> Date: Fri, 13 May 2022 08:47:37 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH] target/arm: Make number of counters in PMCR follow the CPU Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Shuuichirou Ishii , Itaru Kitayama References: <20220513122852.4063586-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220513122852.4063586-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/13/22 05:28, Peter Maydell wrote: > Currently we give all the v7-and-up CPUs a PMU with 4 counters. This > means that we don't provide the 6 counters that are required by the > Arm BSA (Base System Architecture) specification if the CPU supports > the Virtualization extensions. > > Instead of having a single PMCR_NUM_COUNTERS, make each CPU type > specify the PMCR reset value (obtained from the appropriate TRM), and > use the 'N' field of that value to define the number of counters > provided. > > This means that we now supply 6 counters instead of 4 for: > Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72, > Cortex-A76, Neoverse-N1, '-cpu max' > These CPUs remain with 4 counters: > Cortex-A7, Cortex-A8 > This CPU goes down from 4 to 3 counters: > Cortex-R5 > > TODO: A64FX -- I don't know the correct PMCR_EL0 reset value. > > Note that because we now use the PMCR reset value of the specific > implementation, we no longer set the LC bit out of reset. This has > an UNKNOWN value out of reset for all cores with any AArch32 support, > so guest software should be setting it anyway if it wants it. > > This change was originally landed in commit f7fb73b8cdd3f7 (during > the 6.0 release cycle) but was then reverted by commit > 21c2dd77a6aa517 before that release because it did not work with KVM. > This version fixes that by creating the scratch vCPU in > kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature > if KVM supports it, and then only asking KVM for the PMCR_EL0 value > if the vCPU has a PMU. > > Signed-off-by: Peter Maydell > --- > I'd forgotten that we'd dropped this fix in the 6.0 timeframe > and never picked it back up again until Alex reminded me of it... > > Changes since original attempt: > -- rebased > -- fix the code in kvm_arm_get_host_cpu_features() that reads PMCR_EL0 > -- set PMCR value for new CPUs cortex-a76, neoverse-n1 > -- set PMCR value for now-separated-out aarch32 -cpu max > -- TODO comment for a64fx > > Shuuichirou, Itaru: this is another patch where we need to know > an A64FX register value... > --- Reviewed-by: Richard Henderson r~