From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:32810) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URpPq-0003Wt-40 for qemu-devel@nongnu.org; Mon, 15 Apr 2013 15:50:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1URpPo-0002ib-J4 for qemu-devel@nongnu.org; Mon, 15 Apr 2013 15:50:14 -0400 Received: from cantor2.suse.de ([195.135.220.15]:36312 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1URpPo-0002iT-AG for qemu-devel@nongnu.org; Mon, 15 Apr 2013 15:50:12 -0400 Message-ID: <516C59F1.2060209@suse.de> Date: Mon, 15 Apr 2013 21:50:09 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1361817954-8984-1-git-send-email-afaerber@suse.de> <1361817954-8984-8-git-send-email-afaerber@suse.de> In-Reply-To: <1361817954-8984-8-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH qom-cpu v2 7/7] target-cris: Override do_interrupt for pre-v32 CPU cores List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: qemu-devel@nongnu.org Am 25.02.2013 19:45, schrieb Andreas F=C3=A4rber: > Instead of forwarding from cris_cpu_do_interrupt() to do_interruptv10()= , > override CPUClass::do_interrupt with crisv10_cpu_do_interrupt() in the > newly introduced class_init functions. >=20 > Signed-off-by: Andreas F=C3=A4rber > --- > target-cris/cpu-qom.h | 1 + > target-cris/cpu.c | 8 ++++++++ > target-cris/helper.c | 14 ++++++++------ > 3 Dateien ge=C3=A4ndert, 17 Zeilen hinzugef=C3=BCgt(+), 6 Zeilen entfe= rnt(-) Ping? Edgar, I haven't seen an ack or nack for this yet. If it's okay with you, feel free to apply (rebased version available on my qom-cpu-9 branch that I could alternatively include in a pull if you prefer). Thanks, Andreas >=20 > diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h > index deea1d8..03829bd 100644 > --- a/target-cris/cpu-qom.h > +++ b/target-cris/cpu-qom.h > @@ -74,5 +74,6 @@ static inline CRISCPU *cris_env_get_cpu(CPUCRISState = *env) > #define ENV_OFFSET offsetof(CRISCPU, env) > =20 > void cris_cpu_do_interrupt(CPUState *cpu); > +void crisv10_cpu_do_interrupt(CPUState *cpu); > =20 > #endif > diff --git a/target-cris/cpu.c b/target-cris/cpu.c > index 95cbf39..67181e5 100644 > --- a/target-cris/cpu.c > +++ b/target-cris/cpu.c > @@ -169,30 +169,38 @@ static void cris_cpu_initfn(Object *obj) > =20 > static void crisv8_cpu_class_init(ObjectClass *oc, void *data) > { > + CPUClass *cc =3D CPU_CLASS(oc); > CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); > =20 > ccc->vr =3D 8; > + cc->do_interrupt =3D crisv10_cpu_do_interrupt; > } > =20 > static void crisv9_cpu_class_init(ObjectClass *oc, void *data) > { > + CPUClass *cc =3D CPU_CLASS(oc); > CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); > =20 > ccc->vr =3D 9; > + cc->do_interrupt =3D crisv10_cpu_do_interrupt; > } > =20 > static void crisv10_cpu_class_init(ObjectClass *oc, void *data) > { > + CPUClass *cc =3D CPU_CLASS(oc); > CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); > =20 > ccc->vr =3D 10; > + cc->do_interrupt =3D crisv10_cpu_do_interrupt; > } > =20 > static void crisv11_cpu_class_init(ObjectClass *oc, void *data) > { > + CPUClass *cc =3D CPU_CLASS(oc); > CRISCPUClass *ccc =3D CRIS_CPU_CLASS(oc); > =20 > ccc->vr =3D 11; > + cc->do_interrupt =3D crisv10_cpu_do_interrupt; > } > =20 > static void crisv32_cpu_class_init(ObjectClass *oc, void *data) > diff --git a/target-cris/helper.c b/target-cris/helper.c > index e1ef7bc..466cc2f 100644 > --- a/target-cris/helper.c > +++ b/target-cris/helper.c > @@ -45,6 +45,11 @@ void cris_cpu_do_interrupt(CPUState *cs) > env->pregs[PR_ERP] =3D env->pc; > } > =20 > +void crisv10_cpu_do_interrupt(CPUState *cs) > +{ > + cris_cpu_do_interrupt(cs); > +} > + > int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address= , int rw, > int mmu_idx) > { > @@ -109,9 +114,10 @@ int cpu_cris_handle_mmu_fault(CPUCRISState *env, t= arget_ulong address, int rw, > return r; > } > =20 > -static void do_interruptv10(CPUCRISState *env) > +void crisv10_cpu_do_interrupt(CPUState *cs) > { > - D(CPUState *cs =3D CPU(cris_env_get_cpu(env))); > + CRISCPU *cpu =3D CRIS_CPU(cs); > + CPUCRISState *env =3D &cpu->env; > int ex_vec =3D -1; > =20 > D_LOG("exception index=3D%d interrupt_req=3D%d\n", > @@ -171,10 +177,6 @@ void cris_cpu_do_interrupt(CPUState *cs) > CPUCRISState *env =3D &cpu->env; > int ex_vec =3D -1; > =20 > - if (env->pregs[PR_VR] < 32) { > - return do_interruptv10(env); > - } > - > D_LOG("exception index=3D%d interrupt_req=3D%d\n", > env->exception_index, > cs->interrupt_request); --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg