From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:50844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVh8z-0005OY-BY for qemu-devel@nongnu.org; Fri, 26 Apr 2013 07:48:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UVh8x-0002Ua-6D for qemu-devel@nongnu.org; Fri, 26 Apr 2013 07:48:49 -0400 Received: from cantor2.suse.de ([195.135.220.15]:49857 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UVh8w-0002UP-Se for qemu-devel@nongnu.org; Fri, 26 Apr 2013 07:48:47 -0400 Message-ID: <517A699D.3000002@suse.de> Date: Fri, 26 Apr 2013 13:48:45 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1366803094-11619-1-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1366803094-11619-1-git-send-email-edgar.iglesias@gmail.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2] microblaze: Add internal base vectors reg List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: edgar.iglesias@gmail.com Cc: Igor Mammedov , peter.crosthwaite@xilinx.com, qemu-devel@nongnu.org, Eduardo Habkost Hi, Am 24.04.2013 13:31, schrieb edgar.iglesias@gmail.com: > From: "Edgar E. Iglesias" >=20 > Configurable at CPU synthesis/instantiation. >=20 > Signed-off-by: Edgar E. Iglesias > --- >=20 > Peter Crosthwaite commented off-list that it would be a good idea > to make this a device property. I agree but am a bit unsure of > how it should look. Any comments on this attempt? >=20 > v2: > Make base_vectors a CPU/device property. The patch looks good, expect that I don't see any machine or subclass setting that property? If you want to use it from the command line, you would either need to add custom parsing code to -cpu, use -global or dive into experimenting with -device ,xlnx.base-vectors=3Dvalue. Me at least I hav= e been preparing this through code review and fixes but not yet actually tried it for some QOM'ified target since x86 isn't yet. Cheers, Andreas >=20 >=20 > target-microblaze/cpu-qom.h | 1 + > target-microblaze/cpu.c | 8 ++++++++ > target-microblaze/helper.c | 8 ++++---- > 3 files changed, 13 insertions(+), 4 deletions(-) >=20 > diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h > index aa51cf6..ce92a4e 100644 > --- a/target-microblaze/cpu-qom.h > +++ b/target-microblaze/cpu-qom.h > @@ -56,6 +56,7 @@ typedef struct MicroBlazeCPUClass { > typedef struct MicroBlazeCPU { > /*< private >*/ > CPUState parent_obj; > + uint32_t base_vectors; > /*< public >*/ > =20 > CPUMBState env; > diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c > index 0f4293d..404f82c 100644 > --- a/target-microblaze/cpu.c > +++ b/target-microblaze/cpu.c > @@ -22,6 +22,7 @@ > =20 > #include "cpu.h" > #include "qemu-common.h" > +#include "hw/qdev-properties.h" > #include "migration/vmstate.h" > =20 > =20 > @@ -119,6 +120,11 @@ static const VMStateDescription vmstate_mb_cpu =3D= { > .unmigratable =3D 1, > }; > =20 > +static Property mb_properties[] =3D { > + DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vector= s, 0), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > static void mb_cpu_class_init(ObjectClass *oc, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(oc); > @@ -133,6 +139,8 @@ static void mb_cpu_class_init(ObjectClass *oc, void= *data) > =20 > cc->do_interrupt =3D mb_cpu_do_interrupt; > dc->vmsd =3D &vmstate_mb_cpu; > + > + dc->props =3D mb_properties; > } > =20 > static const TypeInfo mb_cpu_type_info =3D { > diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c > index a0416d0..0dd669d 100644 > --- a/target-microblaze/helper.c > +++ b/target-microblaze/helper.c > @@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > env->sregs[SR_ESR], env->iflags); > log_cpu_state_mask(CPU_LOG_INT, env, 0); > env->iflags &=3D ~(IMM_FLAG | D_FLAG); > - env->sregs[SR_PC] =3D 0x20; > + env->sregs[SR_PC] =3D cpu->base_vectors + 0x20; > break; > =20 > case EXCP_MMU: > @@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > env->sregs[SR_PC], env->sregs[SR_EAR], env->= iflags); > log_cpu_state_mask(CPU_LOG_INT, env, 0); > env->iflags &=3D ~(IMM_FLAG | D_FLAG); > - env->sregs[SR_PC] =3D 0x20; > + env->sregs[SR_PC] =3D cpu->base_vectors + 0x20; > break; > =20 > case EXCP_IRQ: > @@ -233,7 +233,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > env->sregs[SR_MSR] |=3D t; > =20 > env->regs[14] =3D env->sregs[SR_PC]; > - env->sregs[SR_PC] =3D 0x10; > + env->sregs[SR_PC] =3D cpu->base_vectors + 0x10; > //log_cpu_state_mask(CPU_LOG_INT, env, 0); > break; > =20 > @@ -252,7 +252,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > if (env->exception_index =3D=3D EXCP_HW_BREAK) { > env->regs[16] =3D env->sregs[SR_PC]; > env->sregs[SR_MSR] |=3D MSR_BIP; > - env->sregs[SR_PC] =3D 0x18; > + env->sregs[SR_PC] =3D cpu->base_vectors + 0x18; > } else > env->sregs[SR_PC] =3D env->btarget; > break; >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg