From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXTOk-0005HU-Ew for qemu-devel@nongnu.org; Wed, 01 May 2013 05:32:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UXTOh-0005ak-BT for qemu-devel@nongnu.org; Wed, 01 May 2013 05:32:26 -0400 Received: from mail-bk0-x22e.google.com ([2a00:1450:4008:c01::22e]:61239) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UXTOh-0005aR-56 for qemu-devel@nongnu.org; Wed, 01 May 2013 05:32:23 -0400 Received: by mail-bk0-f46.google.com with SMTP id e19so580270bku.19 for ; Wed, 01 May 2013 02:32:22 -0700 (PDT) Sender: Richard Henderson Message-ID: <5180E123.9080306@twiddle.net> Date: Wed, 01 May 2013 10:32:19 +0100 From: Richard Henderson MIME-Version: 1.0 References: <1367303797-9561-1-git-send-email-john.rigby@linaro.org> In-Reply-To: <1367303797-9561-1-git-send-email-john.rigby@linaro.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 02/12] ARM: Prepare translation for AArch64 code List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: John Rigby Cc: Peter Maydell , qemu-devel , Alexander Graf On 2013-04-30 07:36, John Rigby wrote: > uint32_t regs[16]; > + > + /* Regs for A64 mode. */ > + uint64_t xregs[31]; > + uint64_t pc; > + uint64_t sp; > + uint32_t pstate; > + uint32_t aarch64_state; /* 1 if CPU is in aarch64 state */ > + How do these registers overlap (or not) in real hardware? Is it possible to union these with the 32-bit state? r~