[Qemu-devel] Patch of consistent VMX cpu flag

qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed

* [Qemu-devel] Patch of consistent VMX cpu flag
@ 2013-05-04  7:59 李春奇 <Arthur Chunqi Li>
  2013-05-04  8:08 ` Jan Kiszka
  0 siblings, 1 reply; 3+ messages in thread
From: 李春奇 <Arthur Chunqi Li> @ 2013-05-04  7:59 UTC (permalink / raw)
  To: qemu-devel; +Cc: Jan Kiszka

[-- Attachment #1: Type: text/plain, Size: 4083 bytes --]

Hi all,
There's a patch for some simulated Intel CPU with default flag of VMX, now
only core(2)duo are with VMX flag by default.

Add default ext_features of CPUID_EXT_VMX to the following CPUs:
kvm64, kvm32, Penryn, Nehalem, Westmere, SandyBridge, Haswell.

Other CPUs of AMD and lower versions of Intel CPU without VMX support don't
add this feature by default.

Patch:

diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index e2302d8..7b659f7 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -490,7 +490,7 @@ static x86_def_t builtin_x86_defs[] = {
             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
             CPUID_PSE36,
         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
-        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
+        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_VMX,
         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
@@ -522,7 +522,7 @@ static x86_def_t builtin_x86_defs[] = {
         .stepping = 1,
         .features = PPRO_FEATURES |
             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
-        .ext_features = CPUID_EXT_SSE3,
+        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_VMX,
         .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
         .ext3_features = 0,
         .xlevel = 0x80000008,
@@ -648,7 +648,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
              CPUID_DE | CPUID_FP87,
         .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3
|
-             CPUID_EXT_SSE3,
+             CPUID_EXT_SSE3 | CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
         .ext3_features = CPUID_EXT3_LAHF_LM,
         .xlevel = 0x8000000A,
@@ -667,7 +667,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
              CPUID_DE | CPUID_FP87,
         .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 |
-             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
+             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 |
CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
CPUID_EXT2_NX,
         .ext3_features = CPUID_EXT3_LAHF_LM,
         .xlevel = 0x8000000A,
@@ -687,7 +687,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_DE | CPUID_FP87,
         .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42
|
              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
-             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
CPUID_EXT2_NX,
         .ext3_features = CPUID_EXT3_LAHF_LM,
         .xlevel = 0x8000000A,
@@ -709,7 +709,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
-             CPUID_EXT_SSE3,
+             CPUID_EXT_SSE3 | CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
|
              CPUID_EXT2_SYSCALL,
         .ext3_features = CPUID_EXT3_LAHF_LM,
@@ -733,7 +733,7 @@ static x86_def_t builtin_x86_defs[] = {
              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA |
CPUID_EXT_MOVBE |
-             CPUID_EXT_PCID,
+             CPUID_EXT_PCID | CPUID_EXT_VMX,
         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
|
              CPUID_EXT2_SYSCALL,
         .ext3_features = CPUID_EXT3_LAHF_LM,

-- 
Arthur Chunqi Li
Department of Computer Science
School of EECS
Peking University
Beijing, China

[-- Attachment #2: Type: text/html, Size: 4976 bytes --]

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [Qemu-devel] Patch of consistent VMX cpu flag
  2013-05-04  7:59 [Qemu-devel] Patch of consistent VMX cpu flag 李春奇 <Arthur Chunqi Li>
@ 2013-05-04  8:08 ` Jan Kiszka
  2013-05-04  8:33   ` Andreas Färber
  0 siblings, 1 reply; 3+ messages in thread
From: Jan Kiszka @ 2013-05-04  8:08 UTC (permalink / raw)
  To: "李春奇 <Arthur Chunqi Li>"; +Cc: qemu-devel

[-- Attachment #1: Type: text/plain, Size: 4588 bytes --]

On 2013-05-04 09:59, 李春奇 <Arthur Chunqi Li> wrote:
> Hi all,
> There's a patch for some simulated Intel CPU with default flag of VMX, now
> only core(2)duo are with VMX flag by default.
> 
> Add default ext_features of CPUID_EXT_VMX to the following CPUs:
> kvm64, kvm32, Penryn, Nehalem, Westmere, SandyBridge, Haswell.
> 
> Other CPUs of AMD and lower versions of Intel CPU without VMX support don't
> add this feature by default.
> 
> Patch:

Please have a look at http://wiki.qemu.org/Contribute/SubmitAPatch
regarding how to format a patch.

Moreover, your mail client had line-wrapping enabled which ruins the
patch. And you are sending mixed plain/html mails, but only plain-text
is acceptable.

Jan

> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index e2302d8..7b659f7 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -490,7 +490,7 @@ static x86_def_t builtin_x86_defs[] = {
>              CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
>              CPUID_PSE36,
>          /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
> -        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
> +        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_VMX,
>          /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
>          .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
>              CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
> @@ -522,7 +522,7 @@ static x86_def_t builtin_x86_defs[] = {
>          .stepping = 1,
>          .features = PPRO_FEATURES |
>              CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
> -        .ext_features = CPUID_EXT_SSE3,
> +        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_VMX,
>          .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
>          .ext3_features = 0,
>          .xlevel = 0x80000008,
> @@ -648,7 +648,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3
> |
> -             CPUID_EXT_SSE3,
> +             CPUID_EXT_SSE3 | CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX |
> CPUID_EXT2_SYSCALL,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
>          .xlevel = 0x8000000A,
> @@ -667,7 +667,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
> CPUID_EXT_SSE41 |
> -             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> +             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 |
> CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
> CPUID_EXT2_NX,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
>          .xlevel = 0x8000000A,
> @@ -687,7 +687,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_DE | CPUID_FP87,
>          .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42
> |
>               CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> -             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> +             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL |
> CPUID_EXT2_NX,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
>          .xlevel = 0x8000000A,
> @@ -709,7 +709,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
>               CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
>               CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
> -             CPUID_EXT_SSE3,
> +             CPUID_EXT_SSE3 | CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
> |
>               CPUID_EXT2_SYSCALL,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
> @@ -733,7 +733,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
>               CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
>               CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA |
> CPUID_EXT_MOVBE |
> -             CPUID_EXT_PCID,
> +             CPUID_EXT_PCID | CPUID_EXT_VMX,
>          .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX
> |
>               CPUID_EXT2_SYSCALL,
>          .ext3_features = CPUID_EXT3_LAHF_LM,
> 



[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 263 bytes --]

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [Qemu-devel] Patch of consistent VMX cpu flag
  2013-05-04  8:08 ` Jan Kiszka
@ 2013-05-04  8:33   ` Andreas Färber
  0 siblings, 0 replies; 3+ messages in thread
From: Andreas Färber @ 2013-05-04  8:33 UTC (permalink / raw)
  To: "李春奇 <Arthur Chunqi Li>"
  Cc: Igor Mammedov, Jan Kiszka, qemu-devel, Eduardo Habkost

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Am 04.05.2013 10:08, schrieb Jan Kiszka:
> On 2013-05-04 09:59, 李春奇 <Arthur Chunqi Li> wrote:
>> Hi all, There's a patch for some simulated Intel CPU with default
>> flag of VMX, now only core(2)duo are with VMX flag by default.
>> 
>> Add default ext_features of CPUID_EXT_VMX to the following CPUs: 
>> kvm64, kvm32, Penryn, Nehalem, Westmere, SandyBridge, Haswell.
>> 
>> Other CPUs of AMD and lower versions of Intel CPU without VMX
>> support don't add this feature by default.
>> 
>> Patch:
> 
> Please have a look at http://wiki.qemu.org/Contribute/SubmitAPatch 
> regarding how to format a patch.
> 
> Moreover, your mail client had line-wrapping enabled which ruins
> the patch. And you are sending mixed plain/html mails, but only
> plain-text is acceptable.

Further, you need to rebase your patch on yesterday's code.

It is not acceptable to simply add CPUID flags to the fields, you need
to assure that pc-i440fx-1.4 and earlier machines maintain the old
values for migration compatibility. See Eduardo's and my pending
series on the mailing list.

Regards,
Andreas

>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c index
>> e2302d8..7b659f7 100644 --- a/target-i386/cpu.c +++
>> b/target-i386/cpu.c @@ -490,7 +490,7 @@ static x86_def_t
>> builtin_x86_defs[] = { CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 
>> CPUID_PSE36, /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ -
>> .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16, +
>> .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_VMX, 
>> /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 
>> .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | 
>> CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, @@ -522,7
>> +522,7 @@ static x86_def_t builtin_x86_defs[] = { .stepping = 1, 
>> .features = PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH |
>> CPUID_MCA | CPUID_PSE36, -        .ext_features =
>> CPUID_EXT_SSE3, +        .ext_features = CPUID_EXT_SSE3 |
>> CPUID_EXT_VMX, .ext2_features = PPRO_FEATURES &
>> CPUID_EXT2_AMD_ALIASES, .ext3_features = 0, .xlevel =
>> 0x80000008, @@ -648,7 +648,7 @@ static x86_def_t
>> builtin_x86_defs[] = { CPUID_MCE | CPUID_PAE | CPUID_MSR |
>> CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, .ext_features =
>> CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | -
>> CPUID_EXT_SSE3, +             CPUID_EXT_SSE3 | CPUID_EXT_VMX, 
>> .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | 
>> CPUID_EXT2_SYSCALL, .ext3_features = CPUID_EXT3_LAHF_LM, .xlevel
>> = 0x8000000A, @@ -667,7 +667,7 @@ static x86_def_t
>> builtin_x86_defs[] = { CPUID_MCE | CPUID_PAE | CPUID_MSR |
>> CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, .ext_features =
>> CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | -
>> CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, +
>> CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 | 
>> CPUID_EXT_VMX, .ext2_features = CPUID_EXT2_LM |
>> CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .ext3_features =
>> CPUID_EXT3_LAHF_LM, .xlevel = 0x8000000A, @@ -687,7 +687,7 @@
>> static x86_def_t builtin_x86_defs[] = { CPUID_DE | CPUID_FP87, 
>> .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT |
>> CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
>> CPUID_EXT_SSSE3 | -             CPUID_EXT_PCLMULQDQ |
>> CPUID_EXT_SSE3, +             CPUID_EXT_PCLMULQDQ |
>> CPUID_EXT_SSE3 | CPUID_EXT_VMX, .ext2_features = CPUID_EXT2_LM |
>> CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .ext3_features =
>> CPUID_EXT3_LAHF_LM, .xlevel = 0x8000000A, @@ -709,7 +709,7 @@
>> static x86_def_t builtin_x86_defs[] = { 
>> CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 
>> CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 
>> CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | -
>> CPUID_EXT_SSE3, +             CPUID_EXT_SSE3 | CPUID_EXT_VMX, 
>> .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
>> CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .ext3_features =
>> CPUID_EXT3_LAHF_LM, @@ -733,7 +733,7 @@ static x86_def_t
>> builtin_x86_defs[] = { CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
>> CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 
>> CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 
>> -             CPUID_EXT_PCID, +             CPUID_EXT_PCID |
>> CPUID_EXT_VMX, .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP
>> | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, .ext3_features =
>> CPUID_EXT3_LAHF_LM,
>> 
> 
> 


- -- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)

iQIcBAEBAgAGBQJRhMftAAoJEPou0S0+fgE/da0P/3B6NbUdfhpkKOP/hZES1xHz
HAAULsF8MsXpJrVnrXOZxFq75NSry/O09HaPb++4Sl+qVxdPNdIj3A2SsgJHODJK
jvYNRkrXmAvtJGUmGfzQ/nFVu72QZgxh9jx0VtTURLYvhSVZI0U8Cj9NybAUzPf8
H1JQCENdZSQb1TMqv6Hg9YV0Ws10EgGOaZsXNvdRcsvn7+YwtXu7OiCymanN7iVB
3jW04WHx6RGrN0q/1sOUWMlHkokA0yVvPQC0/H1E8aBcmdUKdpdM6Wp0nM5sWQd4
K+AGeZ051BAfiTR42lzdQVyW1LIOMK+L1mYjngmpWEBCaQbla3lz4ICgr+lR/tl7
7kFzVz4yAu7vGanwX2HnRlDasag16nsLtAps7xOfpbrBl7Yy2u1EK9k6KIABbc4p
wuAWVk3Xwn1q6jjlPU0b95xoUeJwFCWs1PzKFFhS/zfILnLudV8OSqFBDszxhnqT
vI09OTHD6oViKLFNY3LYrs7bMaf1C1LLbAdf/uXCVssR3+noXeXnKHr70spvKdjN
qs80A6fVPxMzI4IgadPg0TQoIRPmLpZ9wIYjN3Ed22x2CJ0fpA+tQp6k69IYl55s
Cs6UYknfK6X0/r75qq4yGXwByXxqfweQWaLg77JpjAIZczTNG0scEILb3Txo5vzQ
RU7ElB2XoKjRlLxRs8ZC
=shc0
-----END PGP SIGNATURE-----

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2013-05-04  8:33 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-05-04  7:59 [Qemu-devel] Patch of consistent VMX cpu flag 李春奇 <Arthur Chunqi Li>
2013-05-04  8:08 ` Jan Kiszka
2013-05-04  8:33   ` Andreas Färber

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).