From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:58704) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ua4SQ-00035e-6F for qemu-devel@nongnu.org; Wed, 08 May 2013 09:31:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ua4SJ-0000CY-Rx for qemu-devel@nongnu.org; Wed, 08 May 2013 09:30:57 -0400 Sender: Richard Henderson Message-ID: <518A5372.6040408@twiddle.net> Date: Wed, 08 May 2013 08:30:26 -0500 From: Richard Henderson MIME-Version: 1.0 References: <1368019560-25218-1-git-send-email-agraf@suse.de> In-Reply-To: <1368019560-25218-1-git-send-email-agraf@suse.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] PPC: Depend behavior of cmp instructions only on instruction encoding List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Torbjorn Granlund On 2013-05-08 08:26, Alexander Graf wrote: > However, the situation is more complex than that. On 32bit CPUs, L=1 > instructions are either treated identical to L=0 instructions (G4) or > treated as illegal instructions (e500mc). Differenciating these cases > is out of scope for the 1.5 release and will follow afterwards. For now > just treat the 32bit CPU, 64bit cmp case as undefined. Ah ha. Interesting g4/e500 difference. Reviewed-by: Richard Henderson r~