From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>
Subject: Re: [PATCH v2 2/3] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature in gdbstub
Date: Fri, 17 Oct 2025 08:39:32 -0700 [thread overview]
Message-ID: <518e1d4e-abdc-4f03-a60e-9a7c413cb858@linaro.org> (raw)
In-Reply-To: <20251017153027.969016-3-peter.maydell@linaro.org>
On 10/17/25 08:30, Peter Maydell wrote:
> GDB expects the TLS registers to be exposed via org.gnu.gdb.aarch64.tls,
> which will contain either just "tpidr", or else "tpidr" and "tpidr2".
>
> This will be important for SME in future, because the lazy state
> restoration scheme requires GDB to use the TPIDR2 information.
> GDB doesn't currently implement that, but we should provide the
> register via the XML so that we are ready when future GDB versions
> support it.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 1 +
> target/arm/internals.h | 3 ++
> target/arm/gdbstub.c | 6 ++++
> target/arm/gdbstub64.c | 63 ++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 73 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2025-10-17 15:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 15:30 [PATCH v2 0/3] target/arm: Support SME2 in gdbstub Peter Maydell
2025-10-17 15:30 ` [PATCH v2 1/3] target/arm: Implement SME2 support " Peter Maydell
2025-10-17 15:45 ` Richard Henderson
2025-10-20 20:13 ` Philippe Mathieu-Daudé
2025-10-17 15:30 ` [PATCH v2 2/3] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature " Peter Maydell
2025-10-17 15:39 ` Richard Henderson [this message]
2025-10-17 15:30 ` [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers Peter Maydell
2025-10-17 15:41 ` Richard Henderson
2025-10-20 20:14 ` Philippe Mathieu-Daudé
2025-10-23 12:51 ` Peter Maydell
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