* [PATCH v2 1/3] target/arm: Implement SME2 support in gdbstub
2025-10-17 15:30 [PATCH v2 0/3] target/arm: Support SME2 in gdbstub Peter Maydell
@ 2025-10-17 15:30 ` Peter Maydell
2025-10-17 15:45 ` Richard Henderson
2025-10-20 20:13 ` Philippe Mathieu-Daudé
2025-10-17 15:30 ` [PATCH v2 2/3] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature " Peter Maydell
2025-10-17 15:30 ` [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers Peter Maydell
2 siblings, 2 replies; 10+ messages in thread
From: Peter Maydell @ 2025-10-17 15:30 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson, Vacha Bhavsar
For SME2, we need to expose the new ZT0 register in the gdbstub XML.
gdb documents that the requirements are:
> The ‘org.gnu.gdb.aarch64.sme2’ feature is optional. If present,
> then the ‘org.gnu.gdb.aarch64.sme’ feature must also be present.
> The ‘org.gnu.gdb.aarch64.sme2’ feature should contain the
> following:
>
> - ZT0 is a register of 512 bits (64 bytes). It is defined as a
> vector of bytes.
Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
configs/targets/aarch64-bsd-user.mak | 2 +-
configs/targets/aarch64-linux-user.mak | 2 +-
configs/targets/aarch64-softmmu.mak | 2 +-
configs/targets/aarch64_be-linux-user.mak | 2 +-
target/arm/internals.h | 2 +
target/arm/gdbstub.c | 6 +++
target/arm/gdbstub64.c | 52 +++++++++++++++++++++++
gdb-xml/aarch64-sme2.xml | 14 ++++++
8 files changed, 78 insertions(+), 4 deletions(-)
create mode 100644 gdb-xml/aarch64-sme2.xml
diff --git a/configs/targets/aarch64-bsd-user.mak b/configs/targets/aarch64-bsd-user.mak
index f99c73377a9..7f42e060477 100644
--- a/configs/targets/aarch64-bsd-user.mak
+++ b/configs/targets/aarch64-bsd-user.mak
@@ -1,4 +1,4 @@
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml gdb-xml/aarch64-sme2.xml
TARGET_LONG_BITS=64
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
index b779ac3b4a0..bf328b3b80c 100644
--- a/configs/targets/aarch64-linux-user.mak
+++ b/configs/targets/aarch64-linux-user.mak
@@ -1,6 +1,6 @@
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml gdb-xml/aarch64-sme2.xml
TARGET_HAS_BFLT=y
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
index 5dfeb35af90..d14bcfc4900 100644
--- a/configs/targets/aarch64-softmmu.mak
+++ b/configs/targets/aarch64-softmmu.mak
@@ -1,7 +1,7 @@
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
TARGET_KVM_HAVE_GUEST_DEBUG=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml gdb-xml/aarch64-sme2.xml
# needed by boot.c
TARGET_NEED_FDT=y
TARGET_LONG_BITS=64
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
index ef9be02290f..284430add7b 100644
--- a/configs/targets/aarch64_be-linux-user.mak
+++ b/configs/targets/aarch64_be-linux-user.mak
@@ -1,7 +1,7 @@
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
TARGET_BIG_ENDIAN=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml gdb-xml/aarch64-mte.xml gdb-xml/aarch64-sme2.xml
TARGET_HAS_BFLT=y
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/target/arm/internals.h b/target/arm/internals.h
index f539bbe58e1..b8b07e6477c 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1719,6 +1719,8 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg);
int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg);
+int aarch64_gdb_get_sme2_reg(CPUState *cs, GByteArray *buf, int reg);
+int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *buf, int reg);
int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg);
int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 8d2229f5192..1ca3e647a84 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -554,6 +554,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs);
gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg,
aarch64_gdb_set_sme_reg, sme_feature, 0);
+ if (isar_feature_aa64_sme2(&cpu->isar)) {
+ gdb_register_coprocessor(cs, aarch64_gdb_get_sme2_reg,
+ aarch64_gdb_set_sme2_reg,
+ gdb_find_static_feature("aarch64-sme2.xml"),
+ 0);
+ }
}
/*
* Note that we report pauth information via the feature name
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 65d6bbe65fb..5ad00fe771d 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -335,6 +335,58 @@ int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg)
return 0;
}
+int aarch64_gdb_get_sme2_reg(CPUState *cs, GByteArray *buf, int reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ int len = 0;
+
+ switch (reg) {
+ case 0: /* ZT0 */
+ for (int i = 0; i < ARRAY_SIZE(env->za_state.zt0); i += 2) {
+ len += gdb_get_reg128(buf, env->za_state.zt0[i + 1],
+ env->za_state.zt0[i]);
+ }
+ return len;
+ default:
+ /* gdbstub asked for something out of range */
+ qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
+ break;
+ }
+
+ return 0;
+}
+
+int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *buf, int reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ int len = 0;
+
+ switch (reg) {
+ case 0: /* ZT0 */
+ for (int i = 0; i < ARRAY_SIZE(env->za_state.zt0); i += 2) {
+ if (target_big_endian()) {
+ env->za_state.zt0[i + 1] = ldq_p(buf);
+ buf += 8;
+ env->za_state.zt0[i] = ldq_p(buf);
+ } else {
+ env->za_state.zt0[i] = ldq_p(buf);
+ buf += 8;
+ env->za_state.zt0[i + 1] = ldq_p(buf);
+ }
+ buf += 8;
+ len += 16;
+ }
+ return len;
+ default:
+ /* gdbstub asked for something out of range */
+ break;
+ }
+
+ return 0;
+}
+
int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg)
{
ARMCPU *cpu = ARM_CPU(cs);
diff --git a/gdb-xml/aarch64-sme2.xml b/gdb-xml/aarch64-sme2.xml
new file mode 100644
index 00000000000..43911dae160
--- /dev/null
+++ b/gdb-xml/aarch64-sme2.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2025 Linaro Ltd.
+
+ SPDX-License-Identifier: GPL-2.0-or-later
+
+ This is the SME2 ZT0 register. Upstream GDB dynamically generates
+ the XML for this feature, but because the vector is always 64 bytes
+ in size we prefer to use static XML for it.
+ -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.sme2">
+ <vector id="sme2_bv" type="uint8" count="64"/>
+ <reg name="zt0" bitsize="512" type="sme2_bv"/>
+</feature>
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/3] target/arm: Implement SME2 support in gdbstub
2025-10-17 15:30 ` [PATCH v2 1/3] target/arm: Implement SME2 support " Peter Maydell
@ 2025-10-17 15:45 ` Richard Henderson
2025-10-20 20:13 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2025-10-17 15:45 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Vacha Bhavsar
On 10/17/25 08:30, Peter Maydell wrote:
> For SME2, we need to expose the new ZT0 register in the gdbstub XML.
> gdb documents that the requirements are:
>
>> The ‘org.gnu.gdb.aarch64.sme2’ feature is optional. If present,
>> then the ‘org.gnu.gdb.aarch64.sme’ feature must also be present.
>> The ‘org.gnu.gdb.aarch64.sme2’ feature should contain the
>> following:
>>
>> - ZT0 is a register of 512 bits (64 bytes). It is defined as a
>> vector of bytes.
> Implement this.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> configs/targets/aarch64-bsd-user.mak | 2 +-
> configs/targets/aarch64-linux-user.mak | 2 +-
> configs/targets/aarch64-softmmu.mak | 2 +-
> configs/targets/aarch64_be-linux-user.mak | 2 +-
> target/arm/internals.h | 2 +
> target/arm/gdbstub.c | 6 +++
> target/arm/gdbstub64.c | 52 +++++++++++++++++++++++
> gdb-xml/aarch64-sme2.xml | 14 ++++++
> 8 files changed, 78 insertions(+), 4 deletions(-)
> create mode 100644 gdb-xml/aarch64-sme2.xml
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] target/arm: Implement SME2 support in gdbstub
2025-10-17 15:30 ` [PATCH v2 1/3] target/arm: Implement SME2 support " Peter Maydell
2025-10-17 15:45 ` Richard Henderson
@ 2025-10-20 20:13 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 20:13 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Richard Henderson, Vacha Bhavsar
On 17/10/25 17:30, Peter Maydell wrote:
> For SME2, we need to expose the new ZT0 register in the gdbstub XML.
> gdb documents that the requirements are:
>
>> The ‘org.gnu.gdb.aarch64.sme2’ feature is optional. If present,
>> then the ‘org.gnu.gdb.aarch64.sme’ feature must also be present.
>> The ‘org.gnu.gdb.aarch64.sme2’ feature should contain the
>> following:
>>
>> - ZT0 is a register of 512 bits (64 bytes). It is defined as a
>> vector of bytes.
>
> Implement this.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> configs/targets/aarch64-bsd-user.mak | 2 +-
> configs/targets/aarch64-linux-user.mak | 2 +-
> configs/targets/aarch64-softmmu.mak | 2 +-
> configs/targets/aarch64_be-linux-user.mak | 2 +-
> target/arm/internals.h | 2 +
> target/arm/gdbstub.c | 6 +++
> target/arm/gdbstub64.c | 52 +++++++++++++++++++++++
> gdb-xml/aarch64-sme2.xml | 14 ++++++
> 8 files changed, 78 insertions(+), 4 deletions(-)
> create mode 100644 gdb-xml/aarch64-sme2.xml
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature in gdbstub
2025-10-17 15:30 [PATCH v2 0/3] target/arm: Support SME2 in gdbstub Peter Maydell
2025-10-17 15:30 ` [PATCH v2 1/3] target/arm: Implement SME2 support " Peter Maydell
@ 2025-10-17 15:30 ` Peter Maydell
2025-10-17 15:39 ` Richard Henderson
2025-10-17 15:30 ` [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers Peter Maydell
2 siblings, 1 reply; 10+ messages in thread
From: Peter Maydell @ 2025-10-17 15:30 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson, Vacha Bhavsar
GDB expects the TLS registers to be exposed via org.gnu.gdb.aarch64.tls,
which will contain either just "tpidr", or else "tpidr" and "tpidr2".
This will be important for SME in future, because the lazy state
restoration scheme requires GDB to use the TPIDR2 information.
GDB doesn't currently implement that, but we should provide the
register via the XML so that we are ready when future GDB versions
support it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 1 +
target/arm/internals.h | 3 ++
target/arm/gdbstub.c | 6 ++++
target/arm/gdbstub64.c | 63 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 73 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index bf221e6f973..47be3076370 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -941,6 +941,7 @@ struct ArchCPU {
DynamicGDBFeatureInfo dyn_smereg_feature;
DynamicGDBFeatureInfo dyn_m_systemreg_feature;
DynamicGDBFeatureInfo dyn_m_secextreg_feature;
+ DynamicGDBFeatureInfo dyn_tls_feature;
/* Timers used by the generic (architected) timer */
QEMUTimer *gt_timer[NUM_GTIMERS];
diff --git a/target/arm/internals.h b/target/arm/internals.h
index b8b07e6477c..97ff54896e6 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1715,6 +1715,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);
GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg);
+GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cpu, int base_reg);
int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg);
int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg);
@@ -1727,6 +1728,8 @@ int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg);
int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg);
int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg);
+int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg);
+int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg);
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index 1ca3e647a84..8865f27089d 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -583,6 +583,12 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
0);
}
#endif
+
+ /* All AArch64 CPUs have at least TPIDR */
+ gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg,
+ aarch64_gdb_set_tls_reg,
+ arm_gen_dynamic_tls_feature(cs, cs->gdb_num_regs),
+ 0);
#endif
} else {
if (arm_feature(env, ARM_FEATURE_NEON)) {
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 5ad00fe771d..3bc7ff45d57 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -387,6 +387,44 @@ int aarch64_gdb_set_sme2_reg(CPUState *cs, uint8_t *buf, int reg)
return 0;
}
+int aarch64_gdb_get_tls_reg(CPUState *cs, GByteArray *buf, int reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ switch (reg) {
+ case 0: /* TPIDR_EL0 */
+ return gdb_get_reg64(buf, env->cp15.tpidr_el[0]);
+ case 1: /* TPIDR2_EL0 */
+ return gdb_get_reg64(buf, env->cp15.tpidr2_el0);
+ default:
+ /* gdbstub asked for something out of range */
+ break;
+ }
+
+ return 0;
+}
+
+int aarch64_gdb_set_tls_reg(CPUState *cs, uint8_t *buf, int reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ switch (reg) {
+ case 0: /* TPIDR_EL0 */
+ env->cp15.tpidr_el[0] = ldq_p(buf);
+ return 8;
+ case 1: /* TPIDR2_EL0 */
+ env->cp15.tpidr2_el0 = ldq_p(buf);
+ return 8;
+ default:
+ /* gdbstub asked for something out of range */
+ break;
+ }
+
+ return 0;
+}
+
int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -586,6 +624,31 @@ GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg)
return &cpu->dyn_smereg_feature.desc;
}
+GDBFeature *arm_gen_dynamic_tls_feature(CPUState *cs, int base_reg)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ GDBFeatureBuilder builder;
+ int reg = 0;
+
+ gdb_feature_builder_init(&builder, &cpu->dyn_tls_feature.desc,
+ "org.gnu.gdb.aarch64.tls", "tls-registers.xml",
+ base_reg);
+
+ /*
+ * This feature must always have "tpidr", and may also have "tpidr2"
+ * if the CPU has that register.
+ */
+ gdb_feature_builder_append_reg(&builder, "tpidr", 64,
+ reg++, "data_ptr", NULL);
+ if (cpu_isar_feature(aa64_sme, cpu)) {
+ gdb_feature_builder_append_reg(&builder, "tpidr2", 64,
+ reg++, "data_ptr", NULL);
+ }
+ gdb_feature_builder_end(&builder);
+
+ return &cpu->dyn_tls_feature.desc;
+}
+
#ifdef CONFIG_USER_ONLY
int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/3] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature in gdbstub
2025-10-17 15:30 ` [PATCH v2 2/3] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature " Peter Maydell
@ 2025-10-17 15:39 ` Richard Henderson
0 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2025-10-17 15:39 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Vacha Bhavsar
On 10/17/25 08:30, Peter Maydell wrote:
> GDB expects the TLS registers to be exposed via org.gnu.gdb.aarch64.tls,
> which will contain either just "tpidr", or else "tpidr" and "tpidr2".
>
> This will be important for SME in future, because the lazy state
> restoration scheme requires GDB to use the TPIDR2 information.
> GDB doesn't currently implement that, but we should provide the
> register via the XML so that we are ready when future GDB versions
> support it.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/cpu.h | 1 +
> target/arm/internals.h | 3 ++
> target/arm/gdbstub.c | 6 ++++
> target/arm/gdbstub64.c | 63 ++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 73 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers
2025-10-17 15:30 [PATCH v2 0/3] target/arm: Support SME2 in gdbstub Peter Maydell
2025-10-17 15:30 ` [PATCH v2 1/3] target/arm: Implement SME2 support " Peter Maydell
2025-10-17 15:30 ` [PATCH v2 2/3] target/arm: Implement org.gnu.gdb.aarch64.tls XML feature " Peter Maydell
@ 2025-10-17 15:30 ` Peter Maydell
2025-10-17 15:41 ` Richard Henderson
` (2 more replies)
2 siblings, 3 replies; 10+ messages in thread
From: Peter Maydell @ 2025-10-17 15:30 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson, Vacha Bhavsar
Test the SME2 register exposure over gdbstub, in the same way
we already do for SME.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/tcg/aarch64/Makefile.target | 9 ++++++-
tests/tcg/aarch64/gdbstub/test-sme2.py | 36 ++++++++++++++++++++++++++
2 files changed, 44 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/aarch64/gdbstub/test-sme2.py
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 55ce34e45ee..9fa86874534 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -164,7 +164,14 @@ run-gdbstub-sysregs-sme-tile-slice: sysregs
"selected gdb ($(GDB)) does not support SME ZA tile slices")
endif
-EXTRA_RUNS += run-gdbstub-sysregs-sme run-gdbstub-sysregs-sme-tile-slice
+run-gdbstub-sysregs-sme2: sysregs
+ $(call run-test, $@, $(GDB_SCRIPT) \
+ --gdb $(GDB) \
+ --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
+ --bin $< --test $(AARCH64_SRC)/gdbstub/test-sme2.py, \
+ gdbstub SME ZA tile slice support)
+
+EXTRA_RUNS += run-gdbstub-sysregs-sme run-gdbstub-sysregs-sme-tile-slice run-gdbstub-sysregs-sme2
endif
diff --git a/tests/tcg/aarch64/gdbstub/test-sme2.py b/tests/tcg/aarch64/gdbstub/test-sme2.py
new file mode 100644
index 00000000000..a1663fac658
--- /dev/null
+++ b/tests/tcg/aarch64/gdbstub/test-sme2.py
@@ -0,0 +1,36 @@
+#
+# Copyright (C) 2025 Linaro Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Test the SME2 registers are visible and changeable via gdbstub
+#
+# This is launched via tests/guest-debug/run-test.py
+#
+
+import gdb
+from test_gdbstub import main, report
+
+
+def run_test():
+ """Test reads and writes of the SME2 registers"""
+ frame = gdb.selected_frame()
+ rname = "zt0"
+ zt0 = frame.read_register(rname)
+ report(True, "Reading %s" % rname)
+
+ # Writing to the ZT0 register, byte by byte.
+ for i in range(0, 64):
+ cmd = "set $zt0[%d] = 0x01" % (i)
+ gdb.execute(cmd)
+ report(True, "%s" % cmd)
+
+ # Reading from the ZT0 register, byte by byte.
+ for i in range(0, 64):
+ reg = "$zt0[%d]" % (i)
+ v = gdb.parse_and_eval(reg)
+ report(str(v.type) == "uint8_t", "size of %s" % (reg))
+ report(v == 0x1, "%s is 0x%x" % (reg, 0x1))
+
+main(run_test, expected_arch="aarch64")
--
2.43.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers
2025-10-17 15:30 ` [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers Peter Maydell
@ 2025-10-17 15:41 ` Richard Henderson
2025-10-20 20:14 ` Philippe Mathieu-Daudé
2025-10-23 12:51 ` Peter Maydell
2 siblings, 0 replies; 10+ messages in thread
From: Richard Henderson @ 2025-10-17 15:41 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Vacha Bhavsar
On 10/17/25 08:30, Peter Maydell wrote:
> Test the SME2 register exposure over gdbstub, in the same way
> we already do for SME.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> tests/tcg/aarch64/Makefile.target | 9 ++++++-
> tests/tcg/aarch64/gdbstub/test-sme2.py | 36 ++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+), 1 deletion(-)
> create mode 100644 tests/tcg/aarch64/gdbstub/test-sme2.py
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers
2025-10-17 15:30 ` [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers Peter Maydell
2025-10-17 15:41 ` Richard Henderson
@ 2025-10-20 20:14 ` Philippe Mathieu-Daudé
2025-10-23 12:51 ` Peter Maydell
2 siblings, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-20 20:14 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Richard Henderson, Vacha Bhavsar
On 17/10/25 17:30, Peter Maydell wrote:
> Test the SME2 register exposure over gdbstub, in the same way
> we already do for SME.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> tests/tcg/aarch64/Makefile.target | 9 ++++++-
> tests/tcg/aarch64/gdbstub/test-sme2.py | 36 ++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+), 1 deletion(-)
> create mode 100644 tests/tcg/aarch64/gdbstub/test-sme2.py
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers
2025-10-17 15:30 ` [PATCH v2 3/3] tests/tcg/aarch64: Add test case for SME2 gdbstub registers Peter Maydell
2025-10-17 15:41 ` Richard Henderson
2025-10-20 20:14 ` Philippe Mathieu-Daudé
@ 2025-10-23 12:51 ` Peter Maydell
2 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2025-10-23 12:51 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson, Vacha Bhavsar
On Fri, 17 Oct 2025 at 16:30, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Test the SME2 register exposure over gdbstub, in the same way
> we already do for SME.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> +def run_test():
> + """Test reads and writes of the SME2 registers"""
> + frame = gdb.selected_frame()
> + rname = "zt0"
> + zt0 = frame.read_register(rname)
> + report(True, "Reading %s" % rname)
> +
> + # Writing to the ZT0 register, byte by byte.
> + for i in range(0, 64):
> + cmd = "set $zt0[%d] = 0x01" % (i)
> + gdb.execute(cmd)
> + report(True, "%s" % cmd)
These two lines are wrongly indented, and Python will error
out with "unexpected indent". I fixed this up in my local
tree but clearly forgot to commit the change to git before
sending. I'll fix this up in applying them to target-arm.next.
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread