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Date: Thu, 16 May 2013 16:39:20 +0200
From: Claudio Fontana <claudio.fontana@huawei.com>
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Subject: Re: [Qemu-devel] [PATCH 3/3] tcg/aarch64: implement new TCG target
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To: Richard Henderson <rth@twiddle.net>
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>

On 14.05.2013 17:19, Richard Henderson wrote:
> On 05/14/2013 05:25 AM, Peter Maydell wrote:
>>> Yes, I agree. I could not find an image which triggered that
>>>> code path for register rotation amounts.
>> Try PPC : rlwmn will generate a rotl (as will other insns).
>>
> 
> rlwmn will only generate constant rotations; at issue are
> variable rotations.
> 
> Those ought be be generatable with current sources and x86
> 32-bit or 64-bit rotate insns though.  That cleanup was done
> during this release cycle, so if Claudio's testing was on a
> previous release...

Indeed, I was able to test that codepath today after rebasing on current QEMU.

We are working on a new patchset that tries to incorporate the changes discussed up to now.

Thanks,

Claudio