From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46384) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UfYc3-00065w-6G for qemu-devel@nongnu.org; Thu, 23 May 2013 12:43:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UfYbu-0006nk-MI for qemu-devel@nongnu.org; Thu, 23 May 2013 12:43:35 -0400 Received: from mail-gg0-x22a.google.com ([2607:f8b0:4002:c02::22a]:51307) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UfYbu-0006nO-IC for qemu-devel@nongnu.org; Thu, 23 May 2013 12:43:26 -0400 Received: by mail-gg0-f170.google.com with SMTP id s5so1224618ggc.29 for ; Thu, 23 May 2013 09:43:26 -0700 (PDT) Sender: Richard Henderson Message-ID: <519E4729.3060109@twiddle.net> Date: Thu, 23 May 2013 09:43:21 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1369310404-5285-1-git-send-email-peter.maydell@linaro.org> <1369310404-5285-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1369310404-5285-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 01/10] target-arm: Don't use TCGv when we mean TCGv_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: John Rigby , patches@linaro.org, qemu-devel@nongnu.org, Blue Swirl , =?ISO-8859-1?Q?Andreas_F=E4rber?= , Aurelien Jarno On 05/23/2013 04:59 AM, Peter Maydell wrote: > TCGv changes size depending on the compile time value of > TARGET_LONG_BITS. This is useful for generating code for MIPS style > "instructions are the same but the register width changes" CPUs, and > also for the generic bits of QEMU which operate on "width of a > virtual address" values, but mostly in the ARM target code we were > using it purely as a shorthand for "any 32 bit value". > > This needs to change in preparation for AArch64 support, since an > AArch64-capable v8 core will have 64 bit virtual addresses but still > use 32 bit values for the 32 bit instruction set. > > This patch mechanically converts all the occurrences of TCGv, > tcg_temp_new(), tcg_temp_free(), tcg_temp_local_new() and > TCGV_UNUSED() to their explicitly 32 bit counterparts. This is > correct for everything except the arguments to tcg_gen_qemu_{ld,st}*, > which really do need to be TCGv and so will require a 32-to-64 > conversion when building the 32 bit code for AArch64. Those changes > will be in a separate patch for easier review. > > Signed-off-by: Peter Maydell > --- > target-arm/translate.c | 453 ++++++++++++++++++++++++------------------------ > 1 file changed, 229 insertions(+), 224 deletions(-) Reviewed-by: Richard Henderson r~