From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41190) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UjUpa-0005V6-2H for qemu-devel@nongnu.org; Mon, 03 Jun 2013 09:29:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UjUpV-0000s0-9k for qemu-devel@nongnu.org; Mon, 03 Jun 2013 09:29:49 -0400 Received: from lhrrgout.huawei.com ([194.213.3.17]:49354) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UjUpV-0000rt-1B for qemu-devel@nongnu.org; Mon, 03 Jun 2013 09:29:45 -0400 Message-ID: <51AC9A33.9050003@huawei.com> Date: Mon, 3 Jun 2013 15:29:23 +0200 From: Claudio Fontana MIME-Version: 1.0 References: <51AC98CB.1020503@huawei.com> In-Reply-To: <51AC98CB.1020503@huawei.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 3/4] tcg/aarch64: implement byte swap operations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Laurent Desnogues , Jani Kokkonen , "qemu-devel@nongnu.org" , Richard Henderson implement the optional byte swap operations with the dedicated aarch64 instructions. Signed-off-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 32 ++++++++++++++++++++++++++++++++ tcg/aarch64/tcg-target.h | 10 +++++----- 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 3528aa1..aa19a17 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -660,6 +660,20 @@ static inline void tcg_out_goto_label_cond(TCGContext *s, } } +static inline void tcg_out_rev(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +{ + /* using REV 0x5ac00800 */ + unsigned int base = ext ? 0xdac00c00 : 0x5ac00800; + tcg_out32(s, base | rm << 5 | rd); +} + +static inline void tcg_out_rev16(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +{ + /* using REV16 0x5ac00400 */ + unsigned int base = ext ? 0xdac00400 : 0x5ac00400; + tcg_out32(s, base | rm << 5 | rd); +} + #ifdef CONFIG_SOFTMMU #include "exec/softmmu_defs.h" @@ -1012,6 +1026,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, 3); break; + case INDEX_op_bswap64_i64: + ext = 1; /* fall through */ + case INDEX_op_bswap32_i64: + case INDEX_op_bswap32_i32: + tcg_out_rev(s, ext, args[0], args[1]); + break; + case INDEX_op_bswap16_i64: + case INDEX_op_bswap16_i32: + tcg_out_rev16(s, 0, args[0], args[1]); + break; + default: tcg_abort(); /* opcode not implemented */ } @@ -1093,6 +1118,13 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_qemu_st16, { "l", "l" } }, { INDEX_op_qemu_st32, { "l", "l" } }, { INDEX_op_qemu_st64, { "l", "l" } }, + + { INDEX_op_bswap16_i32, { "r", "r" } }, + { INDEX_op_bswap32_i32, { "r", "r" } }, + { INDEX_op_bswap16_i64, { "r", "r" } }, + { INDEX_op_bswap32_i64, { "r", "r" } }, + { INDEX_op_bswap64_i64, { "r", "r" } }, + { -1 }, }; diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 075ab2a..247ef43 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -44,8 +44,8 @@ typedef enum { #define TCG_TARGET_HAS_ext16s_i32 0 #define TCG_TARGET_HAS_ext8u_i32 0 #define TCG_TARGET_HAS_ext16u_i32 0 -#define TCG_TARGET_HAS_bswap16_i32 0 -#define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_bswap16_i32 1 +#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 0 #define TCG_TARGET_HAS_neg_i32 0 #define TCG_TARGET_HAS_rot_i32 1 @@ -68,9 +68,9 @@ typedef enum { #define TCG_TARGET_HAS_ext8u_i64 0 #define TCG_TARGET_HAS_ext16u_i64 0 #define TCG_TARGET_HAS_ext32u_i64 0 -#define TCG_TARGET_HAS_bswap16_i64 0 -#define TCG_TARGET_HAS_bswap32_i64 0 -#define TCG_TARGET_HAS_bswap64_i64 0 +#define TCG_TARGET_HAS_bswap16_i64 1 +#define TCG_TARGET_HAS_bswap32_i64 1 +#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 0 #define TCG_TARGET_HAS_neg_i64 0 #define TCG_TARGET_HAS_rot_i64 1 -- 1.8.1