From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57469) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UkbKK-00049X-Jr for qemu-devel@nongnu.org; Thu, 06 Jun 2013 10:38:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UkbKB-0008C5-1G for qemu-devel@nongnu.org; Thu, 06 Jun 2013 10:38:08 -0400 Received: from host-82-135-62-35.customer.m-online.net ([82.135.62.35]:59446 helo=mail.embedded-brains.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UkbKA-0008BD-MO for qemu-devel@nongnu.org; Thu, 06 Jun 2013 10:37:58 -0400 Received: from [192.168.96.64] (eb0024.eb.z [192.168.96.64]) by mail.embedded-brains.de (Postfix) with ESMTP id 5FB06652CFB for ; Thu, 6 Jun 2013 16:34:29 +0200 (CEST) Message-ID: <51B09DF5.9060606@embedded-brains.de> Date: Thu, 06 Jun 2013 16:34:29 +0200 From: Sebastian Huber MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] SEV and WFE instructions on ARM List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hello, I want to use Qemu to test some SMP code. For this I set up Qemu to fire= up=20 two Cortex-A9 MPCore CPUs. I have the following ticket lock implementati= on: static inline void _ARM_Data_memory_barrier( void ) { __asm__ volatile ( "dmb" : : : "memory" ); } static inline void _ARM_Data_synchronization_barrier( void ) { __asm__ volatile ( "dsb" : : : "memory" ); } static inline void _ARM_Send_event( void ) { __asm__ volatile ( "sev" : : : "memory" ); } static inline void _ARM_Wait_for_event( void ) { __asm__ volatile ( "wfe" : : : "memory" ); } typedef struct { uint32_t next_ticket; uint32_t now_serving; } CPU_SMP_lock_Control; #define CPU_SMP_LOCK_INITIALIZER { 0, 0 } static inline void _CPU_SMP_lock_Acquire( CPU_SMP_lock_Control *lock ) { uint32_t my_ticket; uint32_t next_ticket; uint32_t status; __asm__ volatile ( "1: ldrex %[my_ticket], [%[next_ticket_addr]]\n" "add %[next_ticket], %[my_ticket], #1\n" "strex %[status], %[next_ticket], [%[next_ticket_addr]]\n" "teq %[status], #0\n" "bne 1b" : [my_ticket] "=3D&r" (my_ticket), [next_ticket] "=3D&r" (next_ticket), [status] "=3D&r" (status) : [next_ticket_addr] "r" (&lock->next_ticket) : "cc", "memory" ); while ( my_ticket !=3D lock->now_serving ) { _ARM_Wait_for_event(); } _ARM_Data_memory_barrier(); } static inline void _CPU_SMP_lock_Release( CPU_SMP_lock_Control *lock ) { _ARM_Data_memory_barrier(); ++lock->now_serving; _ARM_Data_synchronization_barrier(); _ARM_Send_event(); } I run the following code on both CPUs: while (1) { _CPU_SMP_lock_Acquire(&lock); ++global_counter; _CPU_SMP_lock_Release(&lock); } It seems that the SEV/WFE instructions are implemented as a nop on Qemu (= see in=20 file "target-arm/translate.c" function gen_nop_hint()). So the simulator= =20 executes the busy wait loop most of the time. Is it possible to trigger = a=20 schedule event in Qemu which stops the simulation on one CPU and selects=20 another CPU instead? --=20 Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine gesch=E4ftliche Mitteilung im Sinne des EHUG.