[Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture

[Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture

[Richard Henderson]

Two prepatory generic tcg patches, to allow non-constant values for
the various TCG_TARGET_HAS_foo macros.

When in patch 3 this gets used, the code inlined in the translators
will be able to check the relevant variable and emit either division
opcode or the call to the division subroutine.

Perhaps more valuable is being able to generate armv7 insns when
running on e.g. an cortex-a15, even when the OS distribution is
built for a more generic armv5.

Tested on an a15, and with various hacks to force each of the unused
code paths to be used.


r~


Richard Henderson (5):
  tcg: Allow non-constant control macros
  tcg: Simplify logic using TCG_OPF_NOT_PRESENT
  tcg-arm: Make use of conditional availability of opcodes for divide
  tcg-arm: Simplify logic in detecting the ARM ISA in use
  tcg-arm: Use AT_PLATFORM to detect the host ISA

 tcg/arm/tcg-target.c | 82 +++++++++++++++++++++++++++-------------------------
 tcg/arm/tcg-target.h | 14 +++++----
 tcg/tcg-opc.h        | 28 ++++++++++--------
 tcg/tcg.c            |  4 +--
 tcg/tcg.h            |  3 +-
 5 files changed, 69 insertions(+), 62 deletions(-)

-- 
1.8.1.4

[Qemu-devel] [PATCH 1/5] tcg: Allow non-constant control macros

[Richard Henderson]

This allows TCG_TARGET_HAS_* to be a variable rather than a constant,
which allows easier support for differing ISA levels for the host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-opc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 4246e9c..db5e6e5 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -40,7 +40,7 @@ DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
 DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
 
-#define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
+#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
 #if TCG_TARGET_REG_BITS == 32
 # define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
 #else
-- 
1.8.1.4

[Qemu-devel] [PATCH 2/5] tcg: Simplify logic using TCG_OPF_NOT_PRESENT

[Richard Henderson]

Expand the definition of "not present" to include "should not be present".
This means we can simplify the logic surrounding the generic tcg opcodes
for which the host backend ought not be providing definitions.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-opc.h | 26 +++++++++++++++-----------
 tcg/tcg.c     |  4 +---
 tcg/tcg.h     |  3 ++-
 3 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index db5e6e5..83f7147 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -27,17 +27,21 @@
  */
 
 /* predefined ops */
-DEF(end, 0, 0, 0, 0) /* must be kept first */
-DEF(nop, 0, 0, 0, 0)
-DEF(nop1, 0, 0, 1, 0)
-DEF(nop2, 0, 0, 2, 0)
-DEF(nop3, 0, 0, 3, 0)
-DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
+DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */
+DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT)
+DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT)
+DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT)
+DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT)
 
-DEF(discard, 1, 0, 0, 0)
+/* variable number of parameters */
+DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT)
+
+DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
+DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
+
+/* variable number of parameters */
+DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
 
-DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
-DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
 
 #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
@@ -166,9 +170,9 @@ DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
 
 /* QEMU specific */
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-DEF(debug_insn_start, 0, 0, 2, 0)
+DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
 #else
-DEF(debug_insn_start, 0, 0, 1, 0)
+DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
 #endif
 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 1d8099c..c7e6567 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1160,9 +1160,7 @@ void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
     i = 0;
     for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
         const TCGOpDef *def = &tcg_op_defs[op];
-        if (op < INDEX_op_call
-            || op == INDEX_op_debug_insn_start
-            || (def->flags & TCG_OPF_NOT_PRESENT)) {
+        if (def->flags & TCG_OPF_NOT_PRESENT) {
             /* Wrong entry in op definitions? */
             if (def->used) {
                 fprintf(stderr, "Invalid op definition for %s\n", def->name);
diff --git a/tcg/tcg.h b/tcg/tcg.h
index df375cf..72b694f 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -593,7 +593,8 @@ enum {
     TCG_OPF_SIDE_EFFECTS = 0x04,
     /* Instruction operands are 64-bits (otherwise 32-bits).  */
     TCG_OPF_64BIT        = 0x08,
-    /* Instruction is optional and not implemented by the host.  */
+    /* Instruction is optional and not implemented by the host, or insn
+       is generic and should not be implemened by the host.  */
     TCG_OPF_NOT_PRESENT  = 0x10,
 };
 
-- 
1.8.1.4

[Qemu-devel] [PATCH 3/5] tcg-arm: Make use of conditional availability of opcodes for divide

[Richard Henderson]

We can now detect and use divide instructions at runtime, rather than
having to restrict their availability to compile-time.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 16 ++++++++++++++--
 tcg/arm/tcg-target.h | 14 ++++++++------
 2 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 3d43412..f6bc165 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
 #endif
 #undef USE_ARMV7_INSTRUCTIONS
 
+#ifndef use_idiv_instructions
+bool use_idiv_instructions;
+#endif
+#ifdef CONFIG_GETAUXVAL
+# include <sys/auxv.h>
+#endif
+
 #ifndef NDEBUG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
     "%r0",
@@ -2041,18 +2048,23 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
     { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
 
-#if TCG_TARGET_HAS_div_i32
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_rem_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
     { INDEX_op_remu_i32, { "r", "r", "r" } },
-#endif
 
     { -1 },
 };
 
 static void tcg_target_init(TCGContext *s)
 {
+#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
+    {
+        unsigned long hwcap = getauxval(AT_HWCAP);
+        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
+    }
+#endif
+
 #if !defined(CONFIG_USER_ONLY)
     /* fail safe */
     if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 3be41cc..4e1a88f 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -49,6 +49,13 @@ typedef enum {
 
 #define TCG_TARGET_NB_REGS 16
 
+#ifdef __ARM_ARCH_EXT_IDIV__
+#define use_idiv_instructions  1
+#else
+extern bool use_idiv_instructions;
+#endif
+
+
 /* used for function call generation */
 #define TCG_REG_CALL_STACK		TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN		8
@@ -73,12 +80,7 @@ typedef enum {
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_movcond_i32      1
 #define TCG_TARGET_HAS_muls2_i32        1
-
-#ifdef __ARM_ARCH_EXT_IDIV__
-#define TCG_TARGET_HAS_div_i32          1
-#else
-#define TCG_TARGET_HAS_div_i32          0
-#endif
+#define TCG_TARGET_HAS_div_i32          use_idiv_instructions
 
 extern bool tcg_target_deposit_valid(int ofs, int len);
 #define TCG_TARGET_deposit_i32_valid  tcg_target_deposit_valid
-- 
1.8.1.4

[Qemu-devel] [PATCH 4/5] tcg-arm: Simplify logic in detecting the ARM ISA in use

[Richard Henderson]

GCC 4.8 defines a handy __ARM_ARCH symbol that we can use, which
will make us nicely forward compatible with ARMv8 AArch32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 62 +++++++++++++++++-----------------------------------
 1 file changed, 20 insertions(+), 42 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index f6bc165..202f1fc 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -22,50 +22,28 @@
  * THE SOFTWARE.
  */
 
-#if defined(__ARM_ARCH_7__) ||  \
-    defined(__ARM_ARCH_7A__) || \
-    defined(__ARM_ARCH_7EM__) || \
-    defined(__ARM_ARCH_7M__) || \
-    defined(__ARM_ARCH_7R__)
-#define USE_ARMV7_INSTRUCTIONS
+/* The __ARM_ARCH define is provided by gcc 4.8.  Construct it otherwise.  */
+#ifndef __ARM_ARCH
+# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
+     || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
+     || defined(__ARM_ARCH_7EM__)
+#  define __ARM_ARCH 7
+# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
+       || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
+       || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
+#  define __ARM_ARCH 6
+# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
+       || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
+       || defined(__ARM_ARCH_5TEJ__)
+#  define __ARM_ARCH 5
+# else
+#  define __ARM_ARCH 4
+# endif
 #endif
 
-#if defined(USE_ARMV7_INSTRUCTIONS) || \
-    defined(__ARM_ARCH_6J__) || \
-    defined(__ARM_ARCH_6K__) || \
-    defined(__ARM_ARCH_6T2__) || \
-    defined(__ARM_ARCH_6Z__) || \
-    defined(__ARM_ARCH_6ZK__)
-#define USE_ARMV6_INSTRUCTIONS
-#endif
-
-#if defined(USE_ARMV6_INSTRUCTIONS) || \
-    defined(__ARM_ARCH_5T__) || \
-    defined(__ARM_ARCH_5TE__) || \
-    defined(__ARM_ARCH_5TEJ__)
-#define USE_ARMV5_INSTRUCTIONS
-#endif
-
-#ifdef USE_ARMV5_INSTRUCTIONS
-static const int use_armv5_instructions = 1;
-#else
-static const int use_armv5_instructions = 0;
-#endif
-#undef USE_ARMV5_INSTRUCTIONS
-
-#ifdef USE_ARMV6_INSTRUCTIONS
-static const int use_armv6_instructions = 1;
-#else
-static const int use_armv6_instructions = 0;
-#endif
-#undef USE_ARMV6_INSTRUCTIONS
-
-#ifdef USE_ARMV7_INSTRUCTIONS
-static const int use_armv7_instructions = 1;
-#else
-static const int use_armv7_instructions = 0;
-#endif
-#undef USE_ARMV7_INSTRUCTIONS
+#define use_armv5_instructions  (__ARM_ARCH >= 5)
+#define use_armv6_instructions  (__ARM_ARCH >= 6)
+#define use_armv7_instructions  (__ARM_ARCH >= 7)
 
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
-- 
1.8.1.4

[Qemu-devel] [PATCH 5/5] tcg-arm: Use AT_PLATFORM to detect the host ISA

[Richard Henderson]

With this we can generate armv7 insns even when the OS compiles for a
lower common denominator.  The macros are arranged so that when we do
compile for a given ISA, all of the runtime checks for that ISA are
optimized away.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 202f1fc..243dedd 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -41,9 +41,11 @@
 # endif
 #endif
 
-#define use_armv5_instructions  (__ARM_ARCH >= 5)
-#define use_armv6_instructions  (__ARM_ARCH >= 6)
-#define use_armv7_instructions  (__ARM_ARCH >= 7)
+static int arm_arch = __ARM_ARCH;
+
+#define use_armv5_instructions  (__ARM_ARCH >= 5 || arm_arch >= 5)
+#define use_armv6_instructions  (__ARM_ARCH >= 6 || arm_arch >= 6)
+#define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)
 
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
@@ -2036,12 +2038,22 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
 static void tcg_target_init(TCGContext *s)
 {
-#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
+#if defined(CONFIG_GETAUXVAL)
+    /* Only probe for the platform and capabilities if we havn't already
+       determined maximum values at compile time.  */
+# if !defined(use_idiv_instructions)
     {
         unsigned long hwcap = getauxval(AT_HWCAP);
         use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
     }
-#endif
+# endif
+    if (__ARM_ARCH < 7) {
+        const char *pl = (const char *)getauxval(AT_PLATFORM);
+        if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
+            arm_arch = pl[1] - '0';
+        }
+    }
+#endif /* GETAUXVAL */
 
 #if !defined(CONFIG_USER_ONLY)
     /* fail safe */
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture

[Richard Henderson]

Ping.


On 06/06/2013 11:05 AM, Richard Henderson wrote:
> Two prepatory generic tcg patches, to allow non-constant values for
> the various TCG_TARGET_HAS_foo macros.
> 
> When in patch 3 this gets used, the code inlined in the translators
> will be able to check the relevant variable and emit either division
> opcode or the call to the division subroutine.
> 
> Perhaps more valuable is being able to generate armv7 insns when
> running on e.g. an cortex-a15, even when the OS distribution is
> built for a more generic armv5.
> 
> Tested on an a15, and with various hacks to force each of the unused
> code paths to be used.
> 
> 
> r~
> 
> 
> Richard Henderson (5):
>   tcg: Allow non-constant control macros
>   tcg: Simplify logic using TCG_OPF_NOT_PRESENT
>   tcg-arm: Make use of conditional availability of opcodes for divide
>   tcg-arm: Simplify logic in detecting the ARM ISA in use
>   tcg-arm: Use AT_PLATFORM to detect the host ISA
> 
>  tcg/arm/tcg-target.c | 82 +++++++++++++++++++++++++++-------------------------
>  tcg/arm/tcg-target.h | 14 +++++----
>  tcg/tcg-opc.h        | 28 ++++++++++--------
>  tcg/tcg.c            |  4 +--
>  tcg/tcg.h            |  3 +-
>  5 files changed, 69 insertions(+), 62 deletions(-)
> 

Re: [Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture

[Richard Henderson]

Ping.

On 06/10/2013 11:42 AM, Richard Henderson wrote:
> Ping.
> 
> 
> On 06/06/2013 11:05 AM, Richard Henderson wrote:
>> Two prepatory generic tcg patches, to allow non-constant values for
>> the various TCG_TARGET_HAS_foo macros.
>>
>> When in patch 3 this gets used, the code inlined in the translators
>> will be able to check the relevant variable and emit either division
>> opcode or the call to the division subroutine.
>>
>> Perhaps more valuable is being able to generate armv7 insns when
>> running on e.g. an cortex-a15, even when the OS distribution is
>> built for a more generic armv5.
>>
>> Tested on an a15, and with various hacks to force each of the unused
>> code paths to be used.
>>
>>
>> r~
>>
>>
>> Richard Henderson (5):
>>   tcg: Allow non-constant control macros
>>   tcg: Simplify logic using TCG_OPF_NOT_PRESENT
>>   tcg-arm: Make use of conditional availability of opcodes for divide
>>   tcg-arm: Simplify logic in detecting the ARM ISA in use
>>   tcg-arm: Use AT_PLATFORM to detect the host ISA
>>
>>  tcg/arm/tcg-target.c | 82 +++++++++++++++++++++++++++-------------------------
>>  tcg/arm/tcg-target.h | 14 +++++----
>>  tcg/tcg-opc.h        | 28 ++++++++++--------
>>  tcg/tcg.c            |  4 +--
>>  tcg/tcg.h            |  3 +-
>>  5 files changed, 69 insertions(+), 62 deletions(-)
>>
> 

Re: [Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture

[Richard Henderson]

Ping 3.

On 06/17/2013 08:56 AM, Richard Henderson wrote:
> Ping.
> 
> On 06/10/2013 11:42 AM, Richard Henderson wrote:
>> Ping.
>>
>>
>> On 06/06/2013 11:05 AM, Richard Henderson wrote:
>>> Two prepatory generic tcg patches, to allow non-constant values for
>>> the various TCG_TARGET_HAS_foo macros.
>>>
>>> When in patch 3 this gets used, the code inlined in the translators
>>> will be able to check the relevant variable and emit either division
>>> opcode or the call to the division subroutine.
>>>
>>> Perhaps more valuable is being able to generate armv7 insns when
>>> running on e.g. an cortex-a15, even when the OS distribution is
>>> built for a more generic armv5.
>>>
>>> Tested on an a15, and with various hacks to force each of the unused
>>> code paths to be used.
>>>
>>>
>>> r~
>>>
>>>
>>> Richard Henderson (5):
>>>   tcg: Allow non-constant control macros
>>>   tcg: Simplify logic using TCG_OPF_NOT_PRESENT
>>>   tcg-arm: Make use of conditional availability of opcodes for divide
>>>   tcg-arm: Simplify logic in detecting the ARM ISA in use
>>>   tcg-arm: Use AT_PLATFORM to detect the host ISA
>>>
>>>  tcg/arm/tcg-target.c | 82 +++++++++++++++++++++++++++-------------------------
>>>  tcg/arm/tcg-target.h | 14 +++++----
>>>  tcg/tcg-opc.h        | 28 ++++++++++--------
>>>  tcg/tcg.c            |  4 +--
>>>  tcg/tcg.h            |  3 +-
>>>  5 files changed, 69 insertions(+), 62 deletions(-)
>>>
>>
>