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From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: Alexander Graf <agraf@suse.de>
Cc: Anthony Liguori <aliguori@us.ibm.com>,
	qemu-devel@nongnu.org,
	Alex Williamson <alex.williamson@redhat.com>,
	qemu-ppc@nongnu.org, David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [Qemu-devel] [PATCH 1/3] spapr pci msi: rework
Date: Fri, 21 Jun 2013 20:52:47 +1000	[thread overview]
Message-ID: <51C4307F.7030201@ozlabs.ru> (raw)
In-Reply-To: <37E1A8FA-6BFA-48D1-AA3E-118671C8638A@suse.de>

On 06/21/2013 08:31 PM, Alexander Graf wrote:
> 
> On 21.06.2013, at 11:22, Alexey Kardashevskiy wrote:
> 
>> Previously every PCI host bridge implemented its own MSI memory window
>> in order to catch msi_notify()/msix_notify() calls from various QEMU
>> MSI-capable devives such as virtio-pci or vfio and redirect them to
>> the guest via qemu_pulse_irq().
> 
> That's how hardware works, no?
> 
>>
>> The encoded MSIMessage used to be encoded as:
>> * .addr - address in a MSI window, this is how QEMU knows which PHB
>> is the message for;
>> * .data - number of a device on a specific PHB and vector number.
>>
>> As a PHB has a destriptor for every device, and every descriptor has
>> first IRQ number and the number of IRQs, it can calculate global IRQ
>> number to use in qemu_pulse_irq().
> 
> How does this work on real hardware?


I do not understand the question, really. Here we are emulating pHyp which
is not real hardware and never pretended to be. Our guests do not touch MSI
records in the config space and use RTAS MSI calls instead.



> 
> 
> Alex
> 
>> However the total number of IRQs is not really big (at the moment it is
>> 1024 IRQs which start from 4096) and the existing system looks overdesigned.
>> The patch simplifies it. Specifically:
>>
>> 1. MSI windows were removed from PHB.
>> 2. Added one memory region for all MSIs.
>> 3. Now MSIMessage::addr is a number of first IRQ of a device,
>> MSIMessage:data is a number of a vector.
>>
>> Putting IRQ number to .data and not using .addr would make it even simpler
>> for MSI-X but it will not work for MSI with multiple vectors unless a first
>> IRQ number of a device is aligned to the MSI vectors number.
>>
>> The simplified scheme also allows easier MSIMessage->IRQ translation
>> for upcoming IRQFD support.
>>
>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> 


-- 
Alexey

  reply	other threads:[~2013-06-21 10:53 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-21  9:22 [Qemu-devel] [PATCH 0/3] RFCv2 kvm irqfd: add directly mapped MSI IRQ support Alexey Kardashevskiy
2013-06-21  9:22 ` [Qemu-devel] [PATCH 1/3] spapr pci msi: rework Alexey Kardashevskiy
2013-06-21 10:31   ` Alexander Graf
2013-06-21 10:52     ` Alexey Kardashevskiy [this message]
2013-06-21 11:58       ` Anthony Liguori
2013-06-21 11:59         ` Alexander Graf
2013-06-21 12:09         ` Benjamin Herrenschmidt
2013-06-21 12:02     ` Benjamin Herrenschmidt
2013-06-21  9:22 ` [Qemu-devel] [PATCH 2/3] KVM: add kvm_arch_irqchip_add_msi_route Alexey Kardashevskiy
2013-06-21 10:33   ` Alexander Graf
2013-06-21 12:03     ` Benjamin Herrenschmidt
2013-06-21 12:05       ` Alexander Graf
2013-06-21 12:10         ` Benjamin Herrenschmidt
2013-06-21 13:46           ` Alexander Graf
2013-06-21 21:54             ` Benjamin Herrenschmidt
2013-06-21 22:12               ` Alexander Graf
2013-06-21 22:21                 ` Benjamin Herrenschmidt
2013-06-21 23:10                   ` Alex Williamson
2013-06-21 23:19                     ` Benjamin Herrenschmidt
2013-06-21  9:22 ` [Qemu-devel] [PATCH 3/3] KVM: PPC: enable irqfd Alexey Kardashevskiy
2013-06-21 17:52   ` Scott Wood
2013-06-22  1:12     ` Alexey Kardashevskiy

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