From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46805) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Upyxg-00018g-8C for qemu-devel@nongnu.org; Fri, 21 Jun 2013 06:53:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Upyxc-0004Er-4t for qemu-devel@nongnu.org; Fri, 21 Jun 2013 06:53:00 -0400 Received: from mail-ie0-x229.google.com ([2607:f8b0:4001:c03::229]:55357) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Upyxc-0004Eg-0f for qemu-devel@nongnu.org; Fri, 21 Jun 2013 06:52:56 -0400 Received: by mail-ie0-f169.google.com with SMTP id 10so19537982ied.28 for ; Fri, 21 Jun 2013 03:52:55 -0700 (PDT) Message-ID: <51C4307F.7030201@ozlabs.ru> Date: Fri, 21 Jun 2013 20:52:47 +1000 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <1371806575-19347-1-git-send-email-aik@ozlabs.ru> <1371806575-19347-2-git-send-email-aik@ozlabs.ru> <37E1A8FA-6BFA-48D1-AA3E-118671C8638A@suse.de> In-Reply-To: <37E1A8FA-6BFA-48D1-AA3E-118671C8638A@suse.de> Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/3] spapr pci msi: rework List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Anthony Liguori , qemu-devel@nongnu.org, Alex Williamson , qemu-ppc@nongnu.org, David Gibson On 06/21/2013 08:31 PM, Alexander Graf wrote: > > On 21.06.2013, at 11:22, Alexey Kardashevskiy wrote: > >> Previously every PCI host bridge implemented its own MSI memory window >> in order to catch msi_notify()/msix_notify() calls from various QEMU >> MSI-capable devives such as virtio-pci or vfio and redirect them to >> the guest via qemu_pulse_irq(). > > That's how hardware works, no? > >> >> The encoded MSIMessage used to be encoded as: >> * .addr - address in a MSI window, this is how QEMU knows which PHB >> is the message for; >> * .data - number of a device on a specific PHB and vector number. >> >> As a PHB has a destriptor for every device, and every descriptor has >> first IRQ number and the number of IRQs, it can calculate global IRQ >> number to use in qemu_pulse_irq(). > > How does this work on real hardware? I do not understand the question, really. Here we are emulating pHyp which is not real hardware and never pretended to be. Our guests do not touch MSI records in the config space and use RTAS MSI calls instead. > > > Alex > >> However the total number of IRQs is not really big (at the moment it is >> 1024 IRQs which start from 4096) and the existing system looks overdesigned. >> The patch simplifies it. Specifically: >> >> 1. MSI windows were removed from PHB. >> 2. Added one memory region for all MSIs. >> 3. Now MSIMessage::addr is a number of first IRQ of a device, >> MSIMessage:data is a number of a vector. >> >> Putting IRQ number to .data and not using .addr would make it even simpler >> for MSI-X but it will not work for MSI with multiple vectors unless a first >> IRQ number of a device is aligned to the MSI vectors number. >> >> The simplified scheme also allows easier MSIMessage->IRQ translation >> for upcoming IRQFD support. >> >> Signed-off-by: Alexey Kardashevskiy > -- Alexey