From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UrKAD-0001Gq-Cp for qemu-devel@nongnu.org; Mon, 24 Jun 2013 23:43:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UrKAA-0001tn-9n for qemu-devel@nongnu.org; Mon, 24 Jun 2013 23:43:29 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:54703) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UrKA9-0001tS-Uu for qemu-devel@nongnu.org; Mon, 24 Jun 2013 23:43:26 -0400 Received: by mail-pa0-f42.google.com with SMTP id rl6so12001441pac.1 for ; Mon, 24 Jun 2013 20:43:24 -0700 (PDT) Sender: Richard Henderson Message-ID: <51C911D8.1000704@twiddle.net> Date: Mon, 24 Jun 2013 20:43:20 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1369936417-16522-1-git-send-email-rth@twiddle.net> <51B61D78.3020609@twiddle.net> <51BF30FF.1090405@twiddle.net> In-Reply-To: <51BF30FF.1090405@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/4] tcg: Split rem requirement from div requirement List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net Ping 3. Pretty please? On 06/17/2013 08:53 AM, Richard Henderson wrote: > Ping. > > On 06/10/2013 11:39 AM, Richard Henderson wrote: >> Ping. >> >> On 05/30/2013 10:53 AM, Richard Henderson wrote: >>> There are several hosts with only a "div" insn. Remainder is computed >>> manually from the quotient and inputs. We can do this generically. >>> >>> Signed-off-by: Richard Henderson >>> --- >>> tcg/arm/tcg-target.h | 2 ++ >>> tcg/hppa/tcg-target.h | 1 + >>> tcg/ia64/tcg-target.h | 2 ++ >>> tcg/mips/tcg-target.h | 1 + >>> tcg/ppc/tcg-target.h | 1 + >>> tcg/ppc64/tcg-target.h | 2 ++ >>> tcg/sparc/tcg-target.h | 2 ++ >>> tcg/tcg-op.h | 32 ++++++++++++++++++++++++++++---- >>> tcg/tcg-opc.h | 8 ++++---- >>> tcg/tcg.h | 3 +++ >>> tcg/tci/tcg-target.h | 2 ++ >>> 11 files changed, 48 insertions(+), 8 deletions(-) >>> >>> diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h >>> index 3be41cc..2c5b4e7 100644 >>> --- a/tcg/arm/tcg-target.h >>> +++ b/tcg/arm/tcg-target.h >>> @@ -76,8 +76,10 @@ typedef enum { >>> >>> #ifdef __ARM_ARCH_EXT_IDIV__ >>> #define TCG_TARGET_HAS_div_i32 1 >>> +#define TCG_TARGET_HAS_rem_i32 1 >>> #else >>> #define TCG_TARGET_HAS_div_i32 0 >>> +#define TCG_TARGET_HAS_rem_i32 0 >>> #endif >>> >>> extern bool tcg_target_deposit_valid(int ofs, int len); >>> diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h >>> index ebd53d9..25467bd 100644 >>> --- a/tcg/hppa/tcg-target.h >>> +++ b/tcg/hppa/tcg-target.h >>> @@ -85,6 +85,7 @@ typedef enum { >>> >>> /* optional instructions */ >>> #define TCG_TARGET_HAS_div_i32 0 >>> +#define TCG_TARGET_HAS_rem_i32 0 >>> #define TCG_TARGET_HAS_rot_i32 1 >>> #define TCG_TARGET_HAS_ext8s_i32 1 >>> #define TCG_TARGET_HAS_ext16s_i32 1 >>> diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h >>> index e3d72ea..f32d519 100644 >>> --- a/tcg/ia64/tcg-target.h >>> +++ b/tcg/ia64/tcg-target.h >>> @@ -104,7 +104,9 @@ typedef enum { >>> >>> /* optional instructions */ >>> #define TCG_TARGET_HAS_div_i32 0 >>> +#define TCG_TARGET_HAS_rem_i32 0 >>> #define TCG_TARGET_HAS_div_i64 0 >>> +#define TCG_TARGET_HAS_rem_i64 0 >>> #define TCG_TARGET_HAS_andc_i32 1 >>> #define TCG_TARGET_HAS_andc_i64 1 >>> #define TCG_TARGET_HAS_bswap16_i32 1 >>> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h >>> index 6155327..a438950 100644 >>> --- a/tcg/mips/tcg-target.h >>> +++ b/tcg/mips/tcg-target.h >>> @@ -79,6 +79,7 @@ typedef enum { >>> >>> /* optional instructions */ >>> #define TCG_TARGET_HAS_div_i32 1 >>> +#define TCG_TARGET_HAS_rem_i32 1 >>> #define TCG_TARGET_HAS_not_i32 1 >>> #define TCG_TARGET_HAS_nor_i32 1 >>> #define TCG_TARGET_HAS_ext8s_i32 1 >>> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h >>> index 17a6bb3..01b880e 100644 >>> --- a/tcg/ppc/tcg-target.h >>> +++ b/tcg/ppc/tcg-target.h >>> @@ -78,6 +78,7 @@ typedef enum { >>> >>> /* optional instructions */ >>> #define TCG_TARGET_HAS_div_i32 1 >>> +#define TCG_TARGET_HAS_rem_i32 1 >>> #define TCG_TARGET_HAS_rot_i32 1 >>> #define TCG_TARGET_HAS_ext8s_i32 1 >>> #define TCG_TARGET_HAS_ext16s_i32 1 >>> diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h >>> index cb77634..7c600f1 100644 >>> --- a/tcg/ppc64/tcg-target.h >>> +++ b/tcg/ppc64/tcg-target.h >>> @@ -76,6 +76,7 @@ typedef enum { >>> >>> /* optional instructions */ >>> #define TCG_TARGET_HAS_div_i32 1 >>> +#define TCG_TARGET_HAS_rem_i32 1 >>> #define TCG_TARGET_HAS_rot_i32 1 >>> #define TCG_TARGET_HAS_ext8s_i32 1 >>> #define TCG_TARGET_HAS_ext16s_i32 1 >>> @@ -96,6 +97,7 @@ typedef enum { >>> #define TCG_TARGET_HAS_muls2_i32 0 >>> >>> #define TCG_TARGET_HAS_div_i64 1 >>> +#define TCG_TARGET_HAS_rem_i64 1 >>> #define TCG_TARGET_HAS_rot_i64 1 >>> #define TCG_TARGET_HAS_ext8s_i64 1 >>> #define TCG_TARGET_HAS_ext16s_i64 1 >>> diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h >>> index b5217be..dab52d7 100644 >>> --- a/tcg/sparc/tcg-target.h >>> +++ b/tcg/sparc/tcg-target.h >>> @@ -86,6 +86,7 @@ typedef enum { >>> >>> /* optional instructions */ >>> #define TCG_TARGET_HAS_div_i32 1 >>> +#define TCG_TARGET_HAS_rem_i32 1 >>> #define TCG_TARGET_HAS_rot_i32 0 >>> #define TCG_TARGET_HAS_ext8s_i32 0 >>> #define TCG_TARGET_HAS_ext16s_i32 0 >>> @@ -109,6 +110,7 @@ typedef enum { >>> >>> #if TCG_TARGET_REG_BITS == 64 >>> #define TCG_TARGET_HAS_div_i64 1 >>> +#define TCG_TARGET_HAS_rem_i64 1 >>> #define TCG_TARGET_HAS_rot_i64 0 >>> #define TCG_TARGET_HAS_ext8s_i64 0 >>> #define TCG_TARGET_HAS_ext16s_i64 0 >>> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h >>> index 94f6043..364964d 100644 >>> --- a/tcg/tcg-op.h >>> +++ b/tcg/tcg-op.h >>> @@ -731,8 +731,14 @@ static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) >>> >>> static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) >>> { >>> - if (TCG_TARGET_HAS_div_i32) { >>> + if (TCG_TARGET_HAS_rem_i32) { >>> tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2); >>> + } else if (TCG_TARGET_HAS_div_i32) { >>> + TCGv_i32 t0 = tcg_temp_new_i32(); >>> + tcg_gen_op3_i32(INDEX_op_div_i32, t0, arg1, arg2); >>> + tcg_gen_mul_i32(t0, t0, arg2); >>> + tcg_gen_sub_i32(ret, arg1, t0); >>> + tcg_temp_free_i32(t0); >>> } else if (TCG_TARGET_HAS_div2_i32) { >>> TCGv_i32 t0 = tcg_temp_new_i32(); >>> tcg_gen_sari_i32(t0, arg1, 31); >>> @@ -769,8 +775,14 @@ static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) >>> >>> static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) >>> { >>> - if (TCG_TARGET_HAS_div_i32) { >>> + if (TCG_TARGET_HAS_rem_i32) { >>> tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2); >>> + } else if (TCG_TARGET_HAS_div_i32) { >>> + TCGv_i32 t0 = tcg_temp_new_i32(); >>> + tcg_gen_op3_i32(INDEX_op_divu_i32, t0, arg1, arg2); >>> + tcg_gen_mul_i32(t0, t0, arg2); >>> + tcg_gen_sub_i32(ret, arg1, t0); >>> + tcg_temp_free_i32(t0); >>> } else if (TCG_TARGET_HAS_div2_i32) { >>> TCGv_i32 t0 = tcg_temp_new_i32(); >>> tcg_gen_movi_i32(t0, 0); >>> @@ -1361,8 +1373,14 @@ static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) >>> >>> static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) >>> { >>> - if (TCG_TARGET_HAS_div_i64) { >>> + if (TCG_TARGET_HAS_rem_i64) { >>> tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2); >>> + } else if (TCG_TARGET_HAS_div_i64) { >>> + TCGv_i64 t0 = tcg_temp_new_i64(); >>> + tcg_gen_op3_i64(INDEX_op_div_i64, t0, arg1, arg2); >>> + tcg_gen_mul_i64(t0, t0, arg2); >>> + tcg_gen_sub_i64(ret, arg1, t0); >>> + tcg_temp_free_i64(t0); >>> } else if (TCG_TARGET_HAS_div2_i64) { >>> TCGv_i64 t0 = tcg_temp_new_i64(); >>> tcg_gen_sari_i64(t0, arg1, 63); >>> @@ -1399,8 +1417,14 @@ static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) >>> >>> static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) >>> { >>> - if (TCG_TARGET_HAS_div_i64) { >>> + if (TCG_TARGET_HAS_rem_i64) { >>> tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2); >>> + } else if (TCG_TARGET_HAS_div_i64) { >>> + TCGv_i64 t0 = tcg_temp_new_i64(); >>> + tcg_gen_op3_i64(INDEX_op_divu_i64, t0, arg1, arg2); >>> + tcg_gen_mul_i64(t0, t0, arg2); >>> + tcg_gen_sub_i64(ret, arg1, t0); >>> + tcg_temp_free_i64(t0); >>> } else if (TCG_TARGET_HAS_div2_i64) { >>> TCGv_i64 t0 = tcg_temp_new_i64(); >>> tcg_gen_movi_i64(t0, 0); >>> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h >>> index 4246e9c..12967fb 100644 >>> --- a/tcg/tcg-opc.h >>> +++ b/tcg/tcg-opc.h >>> @@ -66,8 +66,8 @@ DEF(sub_i32, 1, 2, 0, 0) >>> DEF(mul_i32, 1, 2, 0, 0) >>> DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) >>> DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) >>> -DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) >>> -DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) >>> +DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) >>> +DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) >>> DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) >>> DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) >>> DEF(and_i32, 1, 2, 0, 0) >>> @@ -126,8 +126,8 @@ DEF(sub_i64, 1, 2, 0, IMPL64) >>> DEF(mul_i64, 1, 2, 0, IMPL64) >>> DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) >>> DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) >>> -DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) >>> -DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) >>> +DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) >>> +DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) >>> DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) >>> DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) >>> DEF(and_i64, 1, 2, 0, IMPL64) >>> diff --git a/tcg/tcg.h b/tcg/tcg.h >>> index df375cf..28ca1bd 100644 >>> --- a/tcg/tcg.h >>> +++ b/tcg/tcg.h >>> @@ -60,6 +60,7 @@ typedef uint64_t TCGRegSet; >>> #if TCG_TARGET_REG_BITS == 32 >>> /* Turn some undef macros into false macros. */ >>> #define TCG_TARGET_HAS_div_i64 0 >>> +#define TCG_TARGET_HAS_rem_i64 0 >>> #define TCG_TARGET_HAS_div2_i64 0 >>> #define TCG_TARGET_HAS_rot_i64 0 >>> #define TCG_TARGET_HAS_ext8s_i64 0 >>> @@ -102,11 +103,13 @@ typedef uint64_t TCGRegSet; >>> #define TCG_TARGET_HAS_div2_i32 0 >>> #elif defined(TCG_TARGET_HAS_div2_i32) >>> #define TCG_TARGET_HAS_div_i32 0 >>> +#define TCG_TARGET_HAS_rem_i32 0 >>> #endif >>> #if defined(TCG_TARGET_HAS_div_i64) >>> #define TCG_TARGET_HAS_div2_i64 0 >>> #elif defined(TCG_TARGET_HAS_div2_i64) >>> #define TCG_TARGET_HAS_div_i64 0 >>> +#define TCG_TARGET_HAS_rem_i64 0 >>> #endif >>> >>> typedef enum TCGOpcode { >>> diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h >>> index 0395bbb..9aa1256 100644 >>> --- a/tcg/tci/tcg-target.h >>> +++ b/tcg/tci/tcg-target.h >>> @@ -61,6 +61,7 @@ >>> #define TCG_TARGET_HAS_bswap32_i32 1 >>> /* Not more than one of the next two defines must be 1. */ >>> #define TCG_TARGET_HAS_div_i32 1 >>> +#define TCG_TARGET_HAS_rem_i32 1 >>> #define TCG_TARGET_HAS_div2_i32 0 >>> #define TCG_TARGET_HAS_ext8s_i32 1 >>> #define TCG_TARGET_HAS_ext16s_i32 1 >>> @@ -85,6 +86,7 @@ >>> #define TCG_TARGET_HAS_deposit_i64 1 >>> /* Not more than one of the next two defines must be 1. */ >>> #define TCG_TARGET_HAS_div_i64 0 >>> +#define TCG_TARGET_HAS_rem_i64 0 >>> #define TCG_TARGET_HAS_div2_i64 0 >>> #define TCG_TARGET_HAS_ext8s_i64 1 >>> #define TCG_TARGET_HAS_ext16s_i64 1 >>> >> >