Re: [Qemu-devel] [PATCH 5/5] tcg-arm: Use AT_PLATFORM to detect the host ISA

Re: [Qemu-devel] [PATCH 5/5] tcg-arm: Use AT_PLATFORM to detect the host ISA

[Claudio Fontana]

Richard wrote (eons ago):
> With this we can generate armv7 insns even when the OS compiles for a
> lower common denominator.  The macros are arranged so that when we do
> compile for a given ISA, all of the runtime checks for that ISA are
> optimized away.
> 
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  tcg/arm/tcg-target.c | 22 +++++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index 202f1fc..243dedd 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -41,9 +41,11 @@
>  # endif
>  #endif
>  
> -#define use_armv5_instructions  (__ARM_ARCH >= 5)
> -#define use_armv6_instructions  (__ARM_ARCH >= 6)
> -#define use_armv7_instructions  (__ARM_ARCH >= 7)
> +static int arm_arch = __ARM_ARCH;
> +
> +#define use_armv5_instructions  (__ARM_ARCH >= 5 || arm_arch >= 5)
> +#define use_armv6_instructions  (__ARM_ARCH >= 6 || arm_arch >= 6)
> +#define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)
>  
>  #ifndef use_idiv_instructions
>  bool use_idiv_instructions;
> @@ -2036,12 +2038,22 @@ static const TCGTargetOpDef arm_op_defs[] = {
>  
>  static void tcg_target_init(TCGContext *s)
>  {
> -#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
> +#if defined(CONFIG_GETAUXVAL)
> +    /* Only probe for the platform and capabilities if we havn't already
> +       determined maximum values at compile time.  */
> +# if !defined(use_idiv_instructions)
>      {
>          unsigned long hwcap = getauxval(AT_HWCAP);
>          use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
>      }
> -#endif
> +# endif
> +    if (__ARM_ARCH < 7) {
> +        const char *pl = (const char *)getauxval(AT_PLATFORM);
> +        if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
> +            arm_arch = pl[1] - '0';
> +        }
> +    }
> +#endif /* GETAUXVAL */
>  
>  #if !defined(CONFIG_USER_ONLY)
>      /* fail safe */
> -- 
> 1.8.1.4
> 

this also fails to apply at the moment because of the removal of the 'fail safe' thing.

Claudio

[Qemu-devel] [PATCH 0/5] tcg-arm: Runtime detection of architecture

[Richard Henderson]

Two prepatory generic tcg patches, to allow non-constant values for
the various TCG_TARGET_HAS_foo macros.

When in patch 3 this gets used, the code inlined in the translators
will be able to check the relevant variable and emit either division
opcode or the call to the division subroutine.

Perhaps more valuable is being able to generate armv7 insns when
running on e.g. an cortex-a15, even when the OS distribution is
built for a more generic armv5.

Tested on an a15, and with various hacks to force each of the unused
code paths to be used.


r~


Richard Henderson (5):
  tcg: Allow non-constant control macros
  tcg: Simplify logic using TCG_OPF_NOT_PRESENT
  tcg-arm: Make use of conditional availability of opcodes for divide
  tcg-arm: Simplify logic in detecting the ARM ISA in use
  tcg-arm: Use AT_PLATFORM to detect the host ISA

 tcg/arm/tcg-target.c | 82 +++++++++++++++++++++++++++-------------------------
 tcg/arm/tcg-target.h | 14 +++++----
 tcg/tcg-opc.h        | 28 ++++++++++--------
 tcg/tcg.c            |  4 +--
 tcg/tcg.h            |  3 +-
 5 files changed, 69 insertions(+), 62 deletions(-)

-- 
1.8.1.4

[Qemu-devel] [PATCH 5/5] tcg-arm: Use AT_PLATFORM to detect the host ISA

[Richard Henderson]

With this we can generate armv7 insns even when the OS compiles for a
lower common denominator.  The macros are arranged so that when we do
compile for a given ISA, all of the runtime checks for that ISA are
optimized away.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.c | 22 +++++++++++++++++-----
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 202f1fc..243dedd 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -41,9 +41,11 @@
 # endif
 #endif
 
-#define use_armv5_instructions  (__ARM_ARCH >= 5)
-#define use_armv6_instructions  (__ARM_ARCH >= 6)
-#define use_armv7_instructions  (__ARM_ARCH >= 7)
+static int arm_arch = __ARM_ARCH;
+
+#define use_armv5_instructions  (__ARM_ARCH >= 5 || arm_arch >= 5)
+#define use_armv6_instructions  (__ARM_ARCH >= 6 || arm_arch >= 6)
+#define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)
 
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
@@ -2036,12 +2038,22 @@ static const TCGTargetOpDef arm_op_defs[] = {
 
 static void tcg_target_init(TCGContext *s)
 {
-#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
+#if defined(CONFIG_GETAUXVAL)
+    /* Only probe for the platform and capabilities if we havn't already
+       determined maximum values at compile time.  */
+# if !defined(use_idiv_instructions)
     {
         unsigned long hwcap = getauxval(AT_HWCAP);
         use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);
     }
-#endif
+# endif
+    if (__ARM_ARCH < 7) {
+        const char *pl = (const char *)getauxval(AT_PLATFORM);
+        if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
+            arm_arch = pl[1] - '0';
+        }
+    }
+#endif /* GETAUXVAL */
 
 #if !defined(CONFIG_USER_ONLY)
     /* fail safe */
-- 
1.8.1.4