From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37239) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UsFYa-0003Zk-P1 for qemu-devel@nongnu.org; Thu, 27 Jun 2013 13:01:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UsFXI-0001Ae-KU for qemu-devel@nongnu.org; Thu, 27 Jun 2013 13:00:28 -0400 Received: from cantor2.suse.de ([195.135.220.15]:51339 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UsFXI-00019f-Ba for qemu-devel@nongnu.org; Thu, 27 Jun 2013 12:59:08 -0400 Message-ID: <51CC6F58.6060302@suse.de> Date: Thu, 27 Jun 2013 18:59:04 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1370352705-27590-1-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1370352705-27590-1-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] user-exec.c: Set is_write correctly in the ARM cpu_signal_handler() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org Am 04.06.2013 15:31, schrieb Peter Maydell: > In the ARM implementation of cpu_signal_handler(), set is_write > correctly using the FSR value which the kernel passes us in the > error_code field of uc_mcontext. Since the WnR bit of the FSR was > only introduced in ARMv6, this means that v5 cores will continue > to behave as before this patch, but they are not really supported > as hosts for linux-user mode anyway since they do not have the > modern behaviour for unaligned accesses. >=20 > Signed-off-by: Peter Maydell > --- > Without this linux-user won't work very well. In particular after > fork() bash will segfault, with this in the QEMU_STRACE output > immediately preceding: > sigreturn(18,4390912,1082130608,0,0,0) =3D -1 errno=3D255 (Unknown err= or 255) > at least for PPC and MIPSEL guests. >=20 > user-exec.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) >=20 > diff --git a/user-exec.c b/user-exec.c > index 71bd6c5..336ac70 100644 > --- a/user-exec.c > +++ b/user-exec.c > @@ -20,6 +20,7 @@ > #include "cpu.h" > #include "disas/disas.h" > #include "tcg.h" > +#include "qemu/bitops.h" > =20 > #undef EAX > #undef ECX > @@ -441,8 +442,11 @@ int cpu_signal_handler(int host_signum, void *pinf= o, > #else > pc =3D uc->uc_mcontext.arm_pc; > #endif > - /* XXX: compute is_write */ > - is_write =3D 0; > + > + /* error_code is the FSR value, in which bit 11 is WnR (assuming a= v6 or > + * later processor; on v5 we will always report this as a read). > + */ > + is_write =3D extract32(uc->uc_mcontext.error_code, 11, 1); You seem to be relying on v5 and earlier reading zero here - wondering if that is true for all implementations (OMAP, PXA, etc.)? Safer and closer to the comment might be an explicit check for v6+ if that were possible. Cheers, Andreas > return handle_cpu_signal(pc, (unsigned long)info->si_addr, > is_write, > &uc->uc_sigmask, puc); --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg