From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53963) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Utht7-0001AO-Ak for qemu-devel@nongnu.org; Mon, 01 Jul 2013 13:27:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Utht1-0006V0-7t for qemu-devel@nongnu.org; Mon, 01 Jul 2013 13:27:41 -0400 Received: from mail-gh0-x233.google.com ([2607:f8b0:4002:c05::233]:63368) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Utht0-0006UQ-Uk for qemu-devel@nongnu.org; Mon, 01 Jul 2013 13:27:35 -0400 Received: by mail-gh0-f179.google.com with SMTP id f16so2123844ghb.10 for ; Mon, 01 Jul 2013 10:27:34 -0700 (PDT) Sender: Richard Henderson Message-ID: <51D1BC01.9040209@twiddle.net> Date: Mon, 01 Jul 2013 10:27:29 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1372536117-28167-1-git-send-email-afaerber@suse.de> <1372536117-28167-26-git-send-email-afaerber@suse.de> In-Reply-To: <1372536117-28167-26-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH RFC qom-cpu 25/41] cpu: Move singlestep_enabled field from CPU_COMMON to CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= Cc: Peter Maydell , Gleb Natapov , Anthony Green , Marcelo Tosatti , qemu-devel@nongnu.org, Alexander Graf , Blue Swirl , Max Filippov , Michael Walle , jan.kiszka@web.de, Paul Brook , "Edgar E. Iglesias" , Guan Xuetao , Aurelien Jarno On 06/29/2013 01:01 PM, Andreas Färber wrote: > --- a/target-alpha/translate.c > +++ b/target-alpha/translate.c > @@ -377,10 +377,12 @@ static ExitStatus gen_store_conditional(DisasContext *ctx, int ra, int rb, > > static int use_goto_tb(DisasContext *ctx, uint64_t dest) > { > + CPUState *cs = CPU(ctx->cpu); > + > /* Check for the dest on the same page as the start of the TB. We > also want to suppress goto_tb in the case of single-steping and IO. */ > return (((ctx->tb->pc ^ dest) & TARGET_PAGE_MASK) == 0 > - && !ctx->cpu->env.singlestep_enabled > + && !cs->singlestep_enabled > && !(ctx->tb->cflags & CF_LAST_IO)); > } So continuing the thought from 24/, this stays && !ctx->singlestep_enabled. > > @@ -3379,6 +3381,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, > TranslationBlock *tb, > bool search_pc) > { > + CPUState *cs = CPU(cpu); > CPUAlphaState *env = &cpu->env; > DisasContext ctx, *ctxp = &ctx; > target_ulong pc_start; > @@ -3394,9 +3397,10 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, > gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; > > ctx.tb = tb; > - ctx.cpu = alpha_env_get_cpu(env); > + ctx.cpu = cpu; > ctx.pc = pc_start; > ctx.mem_idx = cpu_mmu_index(env); > + cs = CPU(ctx.cpu); > > /* ??? Every TB begins with unset rounding mode, to be initialized on > the first fp insn of the TB. Alternately we could define a proper > @@ -3453,7 +3457,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, > || tcg_ctx.gen_opc_ptr >= gen_opc_end > || num_insns >= max_insns > || singlestep > - || env->singlestep_enabled)) { > + || cs->singlestep_enabled)) { and this becomes tcg_ctx.singlestep_enabled, either here or in 24/. > ret = EXIT_PC_STALE; > } > } while (ret == NO_EXIT); > @@ -3470,7 +3474,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, > tcg_gen_movi_i64(cpu_pc, ctx.pc); > /* FALLTHRU */ > case EXIT_PC_UPDATED: > - if (env->singlestep_enabled) { > + if (cs->singlestep_enabled) { Likewise. r~